Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7404 |
1 |
|
|
T2 |
6 |
|
T6 |
5 |
|
T7 |
17 |
auto[1] |
20107 |
1 |
|
|
T2 |
11 |
|
T3 |
1 |
|
T6 |
3 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12466 |
1 |
|
|
T2 |
13 |
|
T3 |
1 |
|
T6 |
4 |
auto[1] |
15045 |
1 |
|
|
T2 |
4 |
|
T6 |
4 |
|
T7 |
28 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13190 |
1 |
|
|
T2 |
8 |
|
T6 |
5 |
|
T7 |
25 |
auto[1] |
14321 |
1 |
|
|
T2 |
9 |
|
T3 |
1 |
|
T6 |
3 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1760 |
1 |
|
|
T2 |
3 |
|
T6 |
3 |
|
T7 |
6 |
auto[0] |
auto[0] |
auto[1] |
1682 |
1 |
|
|
T2 |
1 |
|
T7 |
4 |
|
T13 |
9 |
auto[0] |
auto[1] |
auto[0] |
4715 |
1 |
|
|
T2 |
5 |
|
T6 |
1 |
|
T7 |
8 |
auto[0] |
auto[1] |
auto[1] |
4309 |
1 |
|
|
T2 |
4 |
|
T3 |
1 |
|
T7 |
15 |
auto[1] |
auto[0] |
auto[0] |
1717 |
1 |
|
|
T7 |
2 |
|
T13 |
16 |
|
T74 |
1 |
auto[1] |
auto[0] |
auto[1] |
2245 |
1 |
|
|
T2 |
2 |
|
T6 |
2 |
|
T7 |
5 |
auto[1] |
auto[1] |
auto[0] |
4998 |
1 |
|
|
T6 |
1 |
|
T7 |
9 |
|
T8 |
9 |
auto[1] |
auto[1] |
auto[1] |
6085 |
1 |
|
|
T2 |
2 |
|
T6 |
1 |
|
T7 |
12 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7404 |
1 |
|
|
T2 |
6 |
|
T6 |
5 |
|
T7 |
17 |
auto[1] |
20107 |
1 |
|
|
T2 |
11 |
|
T3 |
1 |
|
T6 |
3 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12333 |
1 |
|
|
T2 |
8 |
|
T3 |
1 |
|
T6 |
4 |
auto[1] |
15178 |
1 |
|
|
T2 |
9 |
|
T6 |
4 |
|
T7 |
37 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12992 |
1 |
|
|
T2 |
11 |
|
T6 |
2 |
|
T7 |
29 |
auto[1] |
14519 |
1 |
|
|
T2 |
6 |
|
T3 |
1 |
|
T6 |
6 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1645 |
1 |
|
|
T2 |
2 |
|
T6 |
1 |
|
T7 |
4 |
auto[0] |
auto[0] |
auto[1] |
1750 |
1 |
|
|
T6 |
2 |
|
T7 |
3 |
|
T13 |
11 |
auto[0] |
auto[1] |
auto[0] |
4592 |
1 |
|
|
T2 |
3 |
|
T7 |
11 |
|
T8 |
15 |
auto[0] |
auto[1] |
auto[1] |
4346 |
1 |
|
|
T2 |
3 |
|
T3 |
1 |
|
T6 |
1 |
auto[1] |
auto[0] |
auto[0] |
1747 |
1 |
|
|
T2 |
2 |
|
T7 |
6 |
|
T13 |
13 |
auto[1] |
auto[0] |
auto[1] |
2262 |
1 |
|
|
T2 |
2 |
|
T6 |
2 |
|
T7 |
4 |
auto[1] |
auto[1] |
auto[0] |
5008 |
1 |
|
|
T2 |
4 |
|
T6 |
1 |
|
T7 |
8 |
auto[1] |
auto[1] |
auto[1] |
6161 |
1 |
|
|
T2 |
1 |
|
T6 |
1 |
|
T7 |
19 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7404 |
1 |
|
|
T2 |
6 |
|
T6 |
5 |
|
T7 |
17 |
auto[1] |
20107 |
1 |
|
|
T2 |
11 |
|
T3 |
1 |
|
T6 |
3 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12440 |
1 |
|
|
T2 |
9 |
|
T3 |
1 |
|
T6 |
4 |
auto[1] |
15071 |
1 |
|
|
T2 |
8 |
|
T6 |
4 |
|
T7 |
34 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13176 |
1 |
|
|
T2 |
11 |
|
T6 |
2 |
|
T7 |
33 |
auto[1] |
14335 |
1 |
|
|
T2 |
6 |
|
T3 |
1 |
|
T6 |
6 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1694 |
1 |
|
|
T2 |
3 |
|
T7 |
5 |
|
T13 |
10 |
auto[0] |
auto[0] |
auto[1] |
1711 |
1 |
|
|
T2 |
1 |
|
T6 |
2 |
|
T7 |
2 |
auto[0] |
auto[1] |
auto[0] |
4708 |
1 |
|
|
T2 |
3 |
|
T6 |
1 |
|
T7 |
12 |
auto[0] |
auto[1] |
auto[1] |
4327 |
1 |
|
|
T2 |
2 |
|
T3 |
1 |
|
T6 |
1 |
auto[1] |
auto[0] |
auto[0] |
1742 |
1 |
|
|
T2 |
2 |
|
T7 |
4 |
|
T13 |
10 |
auto[1] |
auto[0] |
auto[1] |
2257 |
1 |
|
|
T6 |
3 |
|
T7 |
6 |
|
T13 |
17 |
auto[1] |
auto[1] |
auto[0] |
5032 |
1 |
|
|
T2 |
3 |
|
T6 |
1 |
|
T7 |
12 |
auto[1] |
auto[1] |
auto[1] |
6040 |
1 |
|
|
T2 |
3 |
|
T7 |
12 |
|
T8 |
8 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7404 |
1 |
|
|
T2 |
6 |
|
T6 |
5 |
|
T7 |
17 |
auto[1] |
20107 |
1 |
|
|
T2 |
11 |
|
T3 |
1 |
|
T6 |
3 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12528 |
1 |
|
|
T2 |
11 |
|
T3 |
1 |
|
T6 |
2 |
auto[1] |
14983 |
1 |
|
|
T2 |
6 |
|
T6 |
6 |
|
T7 |
32 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13200 |
1 |
|
|
T2 |
8 |
|
T3 |
1 |
|
T6 |
5 |
auto[1] |
14311 |
1 |
|
|
T2 |
9 |
|
T6 |
3 |
|
T7 |
28 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1720 |
1 |
|
|
T2 |
3 |
|
T6 |
1 |
|
T7 |
5 |
auto[0] |
auto[0] |
auto[1] |
1739 |
1 |
|
|
T2 |
1 |
|
T6 |
1 |
|
T7 |
3 |
auto[0] |
auto[1] |
auto[0] |
4726 |
1 |
|
|
T2 |
3 |
|
T3 |
1 |
|
T7 |
10 |
auto[0] |
auto[1] |
auto[1] |
4343 |
1 |
|
|
T2 |
4 |
|
T7 |
11 |
|
T8 |
6 |
auto[1] |
auto[0] |
auto[0] |
1714 |
1 |
|
|
T2 |
1 |
|
T6 |
1 |
|
T7 |
5 |
auto[1] |
auto[0] |
auto[1] |
2231 |
1 |
|
|
T2 |
1 |
|
T6 |
2 |
|
T7 |
4 |
auto[1] |
auto[1] |
auto[0] |
5040 |
1 |
|
|
T2 |
1 |
|
T6 |
3 |
|
T7 |
13 |
auto[1] |
auto[1] |
auto[1] |
5998 |
1 |
|
|
T2 |
3 |
|
T7 |
10 |
|
T8 |
17 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7404 |
1 |
|
|
T2 |
6 |
|
T6 |
5 |
|
T7 |
17 |
auto[1] |
20107 |
1 |
|
|
T2 |
11 |
|
T3 |
1 |
|
T6 |
3 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12471 |
1 |
|
|
T2 |
9 |
|
T3 |
1 |
|
T6 |
3 |
auto[1] |
15040 |
1 |
|
|
T2 |
8 |
|
T6 |
5 |
|
T7 |
34 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13006 |
1 |
|
|
T2 |
8 |
|
T3 |
1 |
|
T6 |
3 |
auto[1] |
14505 |
1 |
|
|
T2 |
9 |
|
T6 |
5 |
|
T7 |
29 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1697 |
1 |
|
|
T2 |
3 |
|
T6 |
2 |
|
T7 |
3 |
auto[0] |
auto[0] |
auto[1] |
1738 |
1 |
|
|
T6 |
1 |
|
T7 |
4 |
|
T13 |
15 |
auto[0] |
auto[1] |
auto[0] |
4720 |
1 |
|
|
T2 |
2 |
|
T3 |
1 |
|
T7 |
11 |
auto[0] |
auto[1] |
auto[1] |
4316 |
1 |
|
|
T2 |
4 |
|
T7 |
9 |
|
T8 |
9 |
auto[1] |
auto[0] |
auto[0] |
1654 |
1 |
|
|
T7 |
6 |
|
T13 |
9 |
|
T74 |
1 |
auto[1] |
auto[0] |
auto[1] |
2315 |
1 |
|
|
T2 |
3 |
|
T6 |
2 |
|
T7 |
4 |
auto[1] |
auto[1] |
auto[0] |
4935 |
1 |
|
|
T2 |
3 |
|
T6 |
1 |
|
T7 |
12 |
auto[1] |
auto[1] |
auto[1] |
6136 |
1 |
|
|
T2 |
2 |
|
T6 |
2 |
|
T7 |
12 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7404 |
1 |
|
|
T2 |
6 |
|
T6 |
5 |
|
T7 |
17 |
auto[1] |
20107 |
1 |
|
|
T2 |
11 |
|
T3 |
1 |
|
T6 |
3 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12358 |
1 |
|
|
T2 |
6 |
|
T3 |
1 |
|
T6 |
4 |
auto[1] |
15153 |
1 |
|
|
T2 |
11 |
|
T6 |
4 |
|
T7 |
34 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13068 |
1 |
|
|
T2 |
8 |
|
T6 |
5 |
|
T7 |
30 |
auto[1] |
14443 |
1 |
|
|
T2 |
9 |
|
T3 |
1 |
|
T6 |
3 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1725 |
1 |
|
|
T2 |
2 |
|
T6 |
2 |
|
T7 |
5 |
auto[0] |
auto[0] |
auto[1] |
1712 |
1 |
|
|
T2 |
1 |
|
T6 |
1 |
|
T7 |
1 |
auto[0] |
auto[1] |
auto[0] |
4675 |
1 |
|
|
T6 |
1 |
|
T7 |
10 |
|
T8 |
18 |
auto[0] |
auto[1] |
auto[1] |
4246 |
1 |
|
|
T2 |
3 |
|
T3 |
1 |
|
T7 |
11 |
auto[1] |
auto[0] |
auto[0] |
1689 |
1 |
|
|
T2 |
2 |
|
T7 |
6 |
|
T13 |
9 |
auto[1] |
auto[0] |
auto[1] |
2278 |
1 |
|
|
T2 |
1 |
|
T6 |
2 |
|
T7 |
5 |
auto[1] |
auto[1] |
auto[0] |
4979 |
1 |
|
|
T2 |
4 |
|
T6 |
2 |
|
T7 |
9 |
auto[1] |
auto[1] |
auto[1] |
6207 |
1 |
|
|
T2 |
4 |
|
T7 |
14 |
|
T8 |
12 |