Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	509904	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

193737

1

T1

32

T2

62

T3

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	366377	1			T1	46		T2	109		T3	6
values[0x0]	168174	1			T1	19		T2	57		T3	6
values[0x1]	169090	1			T1	14		T2	67		T3	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	403722	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

299919

1

T1

40

T2

97

T3

8

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3862	1			T5	1		T6	1		T7	1
valid_sources[0x01]	2026	1			T8	1		T13	35		T15	17
valid_sources[0x02]	3519	1			T8	2		T13	34		T74	7
valid_sources[0x03]	2419	1			T7	18		T9	2		T13	27
valid_sources[0x04]	2237	1			T7	8		T8	2		T9	3
valid_sources[0x05]	2225	1			T7	1		T8	7		T9	4
valid_sources[0x06]	2074	1			T5	2		T8	3		T13	35
valid_sources[0x07]	2793	1			T8	3		T13	26		T37	3
valid_sources[0x08]	3352	1			T7	2		T8	1		T9	3
valid_sources[0x09]	6374	1			T7	4		T8	2		T9	1
valid_sources[0x0a]	4055	1			T5	1		T8	8		T9	3
valid_sources[0x0b]	3064	1			T7	26		T8	3		T13	23
valid_sources[0x0c]	2263	1			T7	7		T8	4		T9	3
valid_sources[0x0d]	4025	1			T7	6		T8	1		T9	1
valid_sources[0x0e]	1919	1			T7	15		T13	47		T37	1
valid_sources[0x0f]	2295	1			T5	1		T6	5		T7	5
valid_sources[0x10]	2223	1			T1	3		T7	5		T8	3
valid_sources[0x11]	3221	1			T1	1		T5	2		T6	1
valid_sources[0x12]	2156	1			T5	1		T7	4		T8	2
valid_sources[0x13]	2246	1			T1	2		T8	2		T13	41
valid_sources[0x14]	2434	1			T1	1		T5	1		T8	3
valid_sources[0x15]	3730	1			T7	2		T9	1		T13	18
valid_sources[0x16]	2031	1			T5	1		T7	16		T8	1
valid_sources[0x17]	2189	1			T5	2		T8	1		T9	1
valid_sources[0x18]	1985	1			T1	2		T5	1		T7	5
valid_sources[0x19]	3201	1			T8	1		T13	28		T37	6
valid_sources[0x1a]	8429	1			T1	1		T5	1		T8	2
valid_sources[0x1b]	2032	1			T7	2		T8	3		T13	22
valid_sources[0x1c]	2860	1			T5	3		T7	7		T8	5
valid_sources[0x1d]	2192	1			T5	1		T7	2		T9	1
valid_sources[0x1e]	2425	1			T6	1		T7	4		T13	31
valid_sources[0x1f]	2289	1			T5	2		T8	6		T13	17
valid_sources[0x20]	2773	1			T9	1		T13	41		T74	2
valid_sources[0x21]	2433	1			T4	1		T5	1		T7	8
valid_sources[0x22]	2370	1			T5	1		T8	4		T13	20
valid_sources[0x23]	2226	1			T8	3		T13	38		T37	6
valid_sources[0x24]	2618	1			T8	3		T13	16		T74	1
valid_sources[0x25]	3341	1			T7	8		T8	6		T9	3
valid_sources[0x26]	2201	1			T5	1		T8	6		T9	1
valid_sources[0x27]	2038	1			T5	3		T8	1		T13	34
valid_sources[0x28]	2248	1			T13	19		T37	6		T77	2
valid_sources[0x29]	1891	1			T9	2		T13	42		T37	4
valid_sources[0x2a]	3193	1			T5	1		T6	2		T7	21
valid_sources[0x2b]	2274	1			T1	2		T5	1		T6	2
valid_sources[0x2c]	2874	1			T5	2		T6	2		T7	1
valid_sources[0x2d]	3698	1			T5	3		T7	10		T13	22
valid_sources[0x2e]	2413	1			T7	7		T8	6		T13	24
valid_sources[0x2f]	2078	1			T7	3		T8	6		T9	3
valid_sources[0x30]	2682	1			T6	1		T7	3		T8	5
valid_sources[0x31]	2655	1			T1	2		T8	3		T9	4
valid_sources[0x32]	2488	1			T5	2		T6	1		T7	8
valid_sources[0x33]	2339	1			T8	5		T13	33		T37	4
valid_sources[0x34]	2072	1			T7	8		T8	4		T9	1
valid_sources[0x35]	4543	1			T7	5		T8	2		T9	3
valid_sources[0x36]	2074	1			T1	2		T5	2		T7	12
valid_sources[0x37]	3533	1			T5	1		T6	4		T7	6
valid_sources[0x38]	2451	1			T1	1		T5	2		T8	3
valid_sources[0x39]	2034	1			T8	2		T9	1		T13	18
valid_sources[0x3a]	2552	1			T1	1		T7	4		T8	4
valid_sources[0x3b]	4643	1			T5	1		T7	2		T8	3
valid_sources[0x3c]	2552	1			T5	2		T6	2		T8	10
valid_sources[0x3d]	2808	1			T5	1		T8	4		T9	4
valid_sources[0x3e]	5663	1			T3	22		T5	1		T7	17
valid_sources[0x3f]	3014	1			T7	4		T8	1		T9	1
valid_sources[0x40]	2161	1			T5	1		T7	6		T8	5
valid_sources[0x41]	5070	1			T5	2		T7	2		T8	5
valid_sources[0x42]	4622	1			T5	1		T7	1		T8	6
valid_sources[0x43]	2136	1			T5	2		T7	4		T13	33
valid_sources[0x44]	2274	1			T7	4		T8	5		T13	11
valid_sources[0x45]	2894	1			T6	3		T7	10		T8	5
valid_sources[0x46]	2417	1			T1	2		T5	1		T8	1
valid_sources[0x47]	2906	1			T5	3		T7	11		T8	2
valid_sources[0x48]	3740	1			T5	1		T6	2		T7	11
valid_sources[0x49]	2146	1			T7	1		T8	2		T9	6
valid_sources[0x4a]	3865	1			T7	5		T8	3		T13	24
valid_sources[0x4b]	3405	1			T5	1		T7	16		T13	41
valid_sources[0x4c]	2646	1			T1	3		T7	7		T9	2
valid_sources[0x4d]	2650	1			T5	3		T7	3		T8	3
valid_sources[0x4e]	2141	1			T1	1		T6	2		T7	2
valid_sources[0x4f]	2087	1			T6	4		T7	5		T8	3
valid_sources[0x50]	2208	1			T8	7		T9	2		T13	30
valid_sources[0x51]	2474	1			T5	1		T7	3		T8	2
valid_sources[0x52]	2215	1			T5	1		T7	6		T8	6
valid_sources[0x53]	2162	1			T5	1		T8	2		T9	1
valid_sources[0x54]	2000	1			T6	5		T7	10		T8	4
valid_sources[0x55]	5124	1			T7	3		T8	6		T9	2
valid_sources[0x56]	3050	1			T5	1		T6	1		T8	5
valid_sources[0x57]	2405	1			T5	1		T7	20		T8	1
valid_sources[0x58]	2554	1			T1	1		T5	1		T6	1
valid_sources[0x59]	2084	1			T7	3		T8	4		T9	2
valid_sources[0x5a]	3401	1			T1	4		T7	7		T8	2
valid_sources[0x5b]	3129	1			T8	9		T9	1		T13	33
valid_sources[0x5c]	2276	1			T5	1		T8	9		T13	13
valid_sources[0x5d]	2071	1			T6	2		T7	27		T8	1
valid_sources[0x5e]	2414	1			T7	7		T8	6		T13	12
valid_sources[0x5f]	2112	1			T7	6		T8	6		T9	3
valid_sources[0x60]	1944	1			T5	3		T7	2		T8	13
valid_sources[0x61]	3234	1			T1	1		T5	1		T8	4
valid_sources[0x62]	2056	1			T5	2		T6	1		T8	6
valid_sources[0x63]	2511	1			T8	1		T13	20		T37	7
valid_sources[0x64]	2080	1			T5	1		T7	5		T8	2
valid_sources[0x65]	2416	1			T9	1		T13	18		T37	8
valid_sources[0x66]	2528	1			T8	7		T9	1		T13	39
valid_sources[0x67]	2402	1			T5	1		T6	1		T8	1
valid_sources[0x68]	2452	1			T8	9		T9	1		T13	21
valid_sources[0x69]	3119	1			T5	2		T6	2		T8	3
valid_sources[0x6a]	2157	1			T5	2		T6	1		T7	18
valid_sources[0x6b]	2032	1			T5	1		T7	9		T8	7
valid_sources[0x6c]	2237	1			T5	1		T7	3		T8	3
valid_sources[0x6d]	2652	1			T1	1		T5	2		T7	4
valid_sources[0x6e]	2348	1			T1	2		T8	2		T13	60
valid_sources[0x6f]	2128	1			T5	1		T7	2		T8	3
valid_sources[0x70]	2494	1			T7	6		T8	3		T13	9
valid_sources[0x71]	2069	1			T5	1		T8	10		T9	3
valid_sources[0x72]	3586	1			T5	2		T7	1		T8	9
valid_sources[0x73]	2192	1			T5	1		T8	2		T9	1
valid_sources[0x74]	2974	1			T5	3		T8	1		T9	1
valid_sources[0x75]	2798	1			T5	1		T8	1		T13	6
valid_sources[0x76]	1972	1			T7	4		T8	6		T9	1
valid_sources[0x77]	2502	1			T7	27		T8	7		T13	19
valid_sources[0x78]	2153	1			T5	1		T7	3		T8	4
valid_sources[0x79]	4255	1			T1	1		T13	39		T74	1
valid_sources[0x7a]	3816	1			T5	1		T13	32		T37	2
valid_sources[0x7b]	2366	1			T8	5		T9	2		T13	11
valid_sources[0x7c]	1934	1			T7	4		T8	3		T13	15
valid_sources[0x7d]	2262	1			T1	3		T6	2		T7	1
valid_sources[0x7e]	2134	1			T5	2		T6	3		T7	2
valid_sources[0x7f]	2579	1			T5	1		T6	3		T7	2
valid_sources[0x80]	2021	1			T5	1		T7	4		T8	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

97135

1

T1

26

T2

27

T3

3

values[0x0]

all_enables

biggest_size

62632

1

T1

4

T2

15

T3

1

values[0x1]

all_enables

biggest_size

33970

1

T1

2

T2

20

T3

1