SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35075 | 1 | T8 | 284 | T23 | 411 | T37 | 394 | ||||
others[1] | 35115 | 1 | T8 | 304 | T23 | 398 | T37 | 438 | ||||
others[2] | 34866 | 1 | T8 | 308 | T23 | 393 | T37 | 393 | ||||
others[3] | 58373 | 1 | T8 | 498 | T23 | 669 | T37 | 650 | ||||
false | 19138 | 1 | T7 | 36 | T8 | 50 | T23 | 50 | ||||
true | 29162 | 1 | T1 | 13 | T2 | 1 | T3 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34942 | 1 | T8 | 302 | T23 | 407 | T37 | 412 | ||||
others[1] | 35156 | 1 | T8 | 296 | T23 | 376 | T37 | 407 | ||||
others[2] | 34935 | 1 | T8 | 296 | T23 | 404 | T37 | 380 | ||||
others[3] | 58426 | 1 | T8 | 512 | T23 | 689 | T37 | 667 | ||||
false | 12167 | 1 | T7 | 18 | T8 | 50 | T23 | 50 | ||||
true | 22255 | 1 | T1 | 13 | T2 | 1 | T3 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 721 | 1 | T5 | 1 | T9 | 2 | T36 | 1 | ||||
others[1] | 655 | 1 | T1 | 2 | T5 | 2 | T7 | 1 | ||||
others[2] | 715 | 1 | T1 | 1 | T5 | 1 | T9 | 6 | ||||
others[3] | 1138 | 1 | T1 | 1 | T5 | 3 | T7 | 4 | ||||
false | 13673 | 1 | T1 | 22 | T2 | 1 | T3 | 5 | ||||
true | 4043 | 1 | T1 | 5 | T5 | 9 | T7 | 12 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |