Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T13

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	24668266	6291	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	24668266	265068	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	24668266	10131923	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	24668266	265092	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	24668266	6291	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	24668266	265068	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	24668266	10131923	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	24668266	265092	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24668266	6291	0	0
T3	1422	2	0	0
T4	14942	0	0	0
T5	5130	0	0	0
T6	3142	0	0	0
T7	47312	8	0	0
T8	21975	22	0	0
T9	1909	0	0	0
T10	2152	0	0	0
T13	0	105	0	0
T14	0	77	0	0
T15	0	34	0	0
T21	0	22	0	0
T23	0	21	0	0
T35	1379	0	0	0
T37	0	26	0	0
T38	0	30	0	0
T40	1911	0	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24668266	265068	0	0
T3	1422	176	0	0
T4	14942	0	0	0
T5	5130	0	0	0
T6	3142	0	0	0
T7	47312	344	0	0
T8	21975	544	0	0
T9	1909	0	0	0
T10	2152	0	0	0
T13	0	2762	0	0
T14	0	5195	0	0
T15	0	921	0	0
T21	0	889	0	0
T23	0	424	0	0
T35	1379	0	0	0
T37	0	472	0	0
T38	0	1104	0	0
T40	1911	0	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24668266	10131923	0	0
T2	4630	3261	0	0
T3	1422	551	0	0
T4	14942	0	0	0
T5	5130	0	0	0
T6	3142	1127	0	0
T7	47312	18480	0	0
T8	21975	9875	0	0
T9	1909	0	0	0
T10	2152	0	0	0
T13	0	87050	0	0
T23	0	6283	0	0
T35	1379	0	0	0
T37	0	12046	0	0
T74	0	1786	0	0
T75	0	2627	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24668266	265092	0	0
T3	1422	176	0	0
T4	14942	0	0	0
T5	5130	0	0	0
T6	3142	0	0	0
T7	47312	341	0	0
T8	21975	544	0	0
T9	1909	0	0	0
T10	2152	0	0	0
T13	0	2762	0	0
T14	0	5192	0	0
T15	0	924	0	0
T21	0	889	0	0
T23	0	424	0	0
T35	1379	0	0	0
T37	0	472	0	0
T38	0	1100	0	0
T40	1911	0	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24668266	6291	0	0
T3	1422	2	0	0
T4	14942	0	0	0
T5	5130	0	0	0
T6	3142	0	0	0
T7	47312	8	0	0
T8	21975	22	0	0
T9	1909	0	0	0
T10	2152	0	0	0
T13	0	105	0	0
T14	0	77	0	0
T15	0	34	0	0
T21	0	22	0	0
T23	0	21	0	0
T35	1379	0	0	0
T37	0	26	0	0
T38	0	30	0	0
T40	1911	0	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24668266	265068	0	0
T3	1422	176	0	0
T4	14942	0	0	0
T5	5130	0	0	0
T6	3142	0	0	0
T7	47312	344	0	0
T8	21975	544	0	0
T9	1909	0	0	0
T10	2152	0	0	0
T13	0	2762	0	0
T14	0	5195	0	0
T15	0	921	0	0
T21	0	889	0	0
T23	0	424	0	0
T35	1379	0	0	0
T37	0	472	0	0
T38	0	1104	0	0
T40	1911	0	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24668266	10131923	0	0
T2	4630	3261	0	0
T3	1422	551	0	0
T4	14942	0	0	0
T5	5130	0	0	0
T6	3142	1127	0	0
T7	47312	18480	0	0
T8	21975	9875	0	0
T9	1909	0	0	0
T10	2152	0	0	0
T13	0	87050	0	0
T23	0	6283	0	0
T35	1379	0	0	0
T37	0	12046	0	0
T74	0	1786	0	0
T75	0	2627	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24668266	265092	0	0
T3	1422	176	0	0
T4	14942	0	0	0
T5	5130	0	0	0
T6	3142	0	0	0
T7	47312	341	0	0
T8	21975	544	0	0
T9	1909	0	0	0
T10	2152	0	0	0
T13	0	2762	0	0
T14	0	5192	0	0
T15	0	924	0	0
T21	0	889	0	0
T23	0	424	0	0
T35	1379	0	0	0
T37	0	472	0	0
T38	0	1100	0	0
T40	1911	0	0	0