Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	25253687	15231	0	0
intr_enable_rd_A	25253687	41120	0	0
reset_en_rd_A	25253687	1397	0	0
reset_en_regwen_rd_A	25253687	1270	0	0
wake_info_capture_dis_rd_A	25253687	1112	0	0
wakeup_en_rd_A	25253687	2074	0	0
wakeup_en_regwen_rd_A	25253687	1187	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25253687	15231	0	0
T14	460622	15	0	0
T15	96325	15	0	0
T16	3043	0	0	0
T21	32474	0	0	0
T22	2120	0	0	0
T30	0	15	0	0
T31	0	16	0	0
T32	0	102	0	0
T34	0	24	0	0
T38	0	18	0	0
T39	969	0	0	0
T71	0	14	0	0
T77	6333	0	0	0
T78	3794	0	0	0
T82	2851	0	0	0
T83	5893	0	0	0
T123	0	112	0	0
T124	0	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25253687	41120	0	0
T7	47312	155	0	0
T8	21975	0	0	0
T9	1909	0	0	0
T10	2152	0	0	0
T13	206373	1767	0	0
T14	0	1989	0	0
T22	0	6	0	0
T23	13720	0	0	0
T35	1379	0	0	0
T36	2606	0	0	0
T37	0	194	0	0
T40	1911	0	0	0
T74	4202	21	0	0
T76	0	45	0	0
T77	0	47	0	0
T83	0	9	0	0
T84	0	26	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25253687	1397	0	0
T34	0	15	0	0
T42	4625	0	0	0
T56	5118	0	0	0
T71	341331	2	0	0
T87	0	11	0	0
T88	0	7	0	0
T125	0	4	0	0
T126	0	9	0	0
T127	0	3	0	0
T128	0	2	0	0
T129	0	1	0	0
T130	0	7	0	0
T131	1262	0	0	0
T132	44619	0	0	0
T133	2953	0	0	0
T134	870	0	0	0
T135	15053	0	0	0
T136	8114	0	0	0
T137	10680	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25253687	1270	0	0
T13	206373	6	0	0
T14	460622	0	0	0
T15	96325	0	0	0
T16	3043	0	0	0
T30	0	2	0	0
T34	0	18	0	0
T37	21533	0	0	0
T39	969	0	0	0
T74	4202	0	0	0
T75	4451	0	0	0
T76	9256	0	0	0
T77	6333	0	0	0
T87	0	6	0	0
T88	0	19	0	0
T125	0	5	0	0
T126	0	10	0	0
T127	0	5	0	0
T129	0	9	0	0
T130	0	9	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25253687	1112	0	0
T30	415931	10	0	0
T31	407788	0	0	0
T32	651653	0	0	0
T33	6006	0	0	0
T34	233610	11	0	0
T87	0	10	0	0
T88	0	13	0	0
T99	51336	0	0	0
T126	0	1	0	0
T127	0	10	0	0
T129	0	8	0	0
T130	0	6	0	0
T138	0	2	0	0
T139	0	4	0	0
T140	5593	0	0	0
T141	22859	0	0	0
T142	4934	0	0	0
T143	961	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25253687	2074	0	0
T13	206373	8	0	0
T14	460622	0	0	0
T15	96325	0	0	0
T16	3043	0	0	0
T34	0	10	0	0
T37	21533	0	0	0
T39	969	0	0	0
T74	4202	0	0	0
T75	4451	0	0	0
T76	9256	0	0	0
T77	6333	0	0	0
T87	0	8	0	0
T88	0	5	0	0
T125	0	3	0	0
T127	0	1	0	0
T128	0	2	0	0
T129	0	7	0	0
T130	0	9	0	0
T139	0	9	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25253687	1187	0	0
T13	206373	1	0	0
T14	460622	3	0	0
T15	96325	0	0	0
T16	3043	0	0	0
T30	0	7	0	0
T34	0	21	0	0
T37	21533	0	0	0
T39	969	0	0	0
T74	4202	0	0	0
T75	4451	0	0	0
T76	9256	0	0	0
T77	6333	0	0	0
T87	0	12	0	0
T88	0	16	0	0
T125	0	3	0	0
T126	0	2	0	0
T129	0	14	0	0
T138	0	5	0	0