Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	74004798	145909	0	0
StatusRise_A	74004798	162799	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74004798	145909	0	0
T1	12573	54	0	0
T2	13890	43	0	0
T3	4266	12	0	0
T4	44826	3	0	0
T5	15390	66	0	0
T6	9426	18	0	0
T7	141936	284	0	0
T8	65925	226	0	0
T9	5727	12	0	0
T10	6456	0	0	0
T35	0	21	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74004798	162799	0	0
T1	12573	60	0	0
T2	13890	45	0	0
T3	4266	15	0	0
T4	44826	6	0	0
T5	15390	72	0	0
T6	9426	20	0	0
T7	141936	311	0	0
T8	65925	229	0	0
T9	5727	15	0	0
T10	6456	18	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24668266	54133	0	0
StatusRise_A	24668266	60237	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24668266	54133	0	0
T1	4191	18	0	0
T2	4630	17	0	0
T3	1422	4	0	0
T4	14942	1	0	0
T5	5130	22	0	0
T6	3142	8	0	0
T7	47312	106	0	0
T8	21975	89	0	0
T9	1909	4	0	0
T10	2152	0	0	0
T35	0	7	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24668266	60237	0	0
T1	4191	20	0	0
T2	4630	18	0	0
T3	1422	5	0	0
T4	14942	2	0	0
T5	5130	24	0	0
T6	3142	9	0	0
T7	47312	116	0	0
T8	21975	90	0	0
T9	1909	5	0	0
T10	2152	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24668266	54134	0	0
StatusRise_A	24668266	60238	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24668266	54134	0	0
T1	4191	18	0	0
T2	4630	17	0	0
T3	1422	4	0	0
T4	14942	1	0	0
T5	5130	22	0	0
T6	3142	8	0	0
T7	47312	106	0	0
T8	21975	89	0	0
T9	1909	4	0	0
T10	2152	0	0	0
T35	0	7	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24668266	60238	0	0
T1	4191	20	0	0
T2	4630	18	0	0
T3	1422	5	0	0
T4	14942	2	0	0
T5	5130	24	0	0
T6	3142	9	0	0
T7	47312	116	0	0
T8	21975	90	0	0
T9	1909	5	0	0
T10	2152	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24668266	37642	0	0
StatusRise_A	24668266	42324	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24668266	37642	0	0
T1	4191	18	0	0
T2	4630	9	0	0
T3	1422	4	0	0
T4	14942	1	0	0
T5	5130	22	0	0
T6	3142	2	0	0
T7	47312	72	0	0
T8	21975	48	0	0
T9	1909	4	0	0
T10	2152	0	0	0
T35	0	7	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24668266	42324	0	0
T1	4191	20	0	0
T2	4630	9	0	0
T3	1422	5	0	0
T4	14942	2	0	0
T5	5130	24	0	0
T6	3142	2	0	0
T7	47312	79	0	0
T8	21975	49	0	0
T9	1909	5	0	0
T10	2152	6	0	0