Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	24668864	5180	0	0
EscTimeoutStoppedByClReset_A	24668266	3480062	0	0
EscTimeoutTriggersReset_A	4986609	313	0	0
RomAllowActiveState_A	24668266	59844	0	0
RomAllowCheckGoodState_A	24668266	59902	0	0
RomBlockActiveState_A	24668266	31160	0	0
RomBlockCheckGoodState_A	24668266	428457	0	0
RomIntgChkDisFalse_A	24668266	24035231	0	0
RomIntgChkDisTrue_A	24668266	107201	0	0
RstreqChkEsctimeout_A	24668266	4325	0	0
RstreqChkFsmterm_A	24668266	160	0	0
RstreqChkGlbesc_A	24668266	4325	0	0
RstreqChkMainpd_A	24668266	1002933	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24668864	5180	0	0
T4	14943	10	0	0
T5	5131	0	0	0
T6	3143	0	0	0
T7	47313	0	0	0
T8	21976	0	0	0
T9	1910	0	0	0
T10	2152	0	0	0
T11	0	39	0	0
T12	0	56	0	0
T23	13721	0	0	0
T35	1380	0	0	0
T40	1911	0	0	0
T135	0	56	0	0
T144	0	37	0	0
T145	0	19	0	0
T146	0	37	0	0
T147	0	144	0	0
T148	0	95	0	0
T149	0	27	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24668266	3480062	0	0
T1	4191	367	0	0
T2	4630	295	0	0
T3	1422	41	0	0
T4	14942	19	0	0
T5	5130	612	0	0
T6	3142	467	0	0
T7	47312	7791	0	0
T8	21975	3358	0	0
T9	1909	52	0	0
T10	2152	104	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4986609	313	0	0
T4	3161	5	0	0
T5	755	0	0	0
T6	1146	0	0	0
T7	8581	0	0	0
T8	8615	0	0	0
T9	760	0	0	0
T10	402	0	0	0
T11	0	3	0	0
T12	0	3	0	0
T23	8857	0	0	0
T35	470	0	0	0
T40	172	0	0	0
T135	0	3	0	0
T144	0	2	0	0
T145	0	2	0	0
T146	0	3	0	0
T150	0	10	0	0
T151	0	4	0	0
T152	0	3	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24668266	59844	0	0
T1	4191	13	0	0
T2	4630	18	0	0
T3	1422	5	0	0
T4	14942	2	0	0
T5	5130	24	0	0
T6	3142	9	0	0
T7	47312	116	0	0
T8	21975	90	0	0
T9	1909	5	0	0
T10	2152	6	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24668266	59902	0	0
T1	4191	14	0	0
T2	4630	18	0	0
T3	1422	5	0	0
T4	14942	2	0	0
T5	5130	24	0	0
T6	3142	9	0	0
T7	47312	116	0	0
T8	21975	90	0	0
T9	1909	5	0	0
T10	2152	6	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24668266	31160	0	0
T8	21975	27	0	0
T9	1909	0	0	0
T10	2152	0	0	0
T13	206373	0	0	0
T22	0	360	0	0
T23	13720	0	0	0
T35	1379	0	0	0
T36	2606	0	0	0
T37	0	8	0	0
T40	1911	0	0	0
T74	4202	0	0	0
T75	4451	0	0	0
T153	0	3	0	0
T154	0	1495	0	0
T155	0	384	0	0
T156	0	106	0	0
T157	0	591	0	0
T158	0	1451	0	0
T159	0	897	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24668266	428457	0	0
T7	47312	413	0	0
T8	21975	1253	0	0
T9	1909	0	0	0
T10	2152	0	0	0
T13	206373	4523	0	0
T14	0	3163	0	0
T15	0	1768	0	0
T21	0	2202	0	0
T22	0	85	0	0
T23	13720	932	0	0
T35	1379	0	0	0
T36	2606	0	0	0
T37	0	940	0	0
T38	0	1559	0	0
T40	1911	0	0	0
T74	4202	0	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24668266	24035231	0	0
T1	4191	3179	0	0
T2	4630	4546	0	0
T3	1422	1046	0	0
T4	14942	14850	0	0
T5	5130	5017	0	0
T6	3142	3052	0	0
T7	47312	46502	0	0
T8	21975	21011	0	0
T9	1909	1810	0	0
T10	2152	1789	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24668266	107201	0	0
T8	21975	882	0	0
T9	1909	0	0	0
T10	2152	0	0	0
T13	206373	0	0	0
T21	0	1015	0	0
T22	0	860	0	0
T23	13720	0	0	0
T35	1379	0	0	0
T36	2606	0	0	0
T40	1911	0	0	0
T74	4202	0	0	0
T75	4451	0	0	0
T154	0	2403	0	0
T155	0	397	0	0
T156	0	29	0	0
T157	0	1289	0	0
T158	0	290	0	0
T160	0	3184	0	0
T161	0	1218	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24668266	4325	0	0
T1	4191	9	0	0
T2	4630	0	0	0
T3	1422	0	0	0
T4	14942	1	0	0
T5	5130	5	0	0
T6	3142	0	0	0
T7	47312	14	0	0
T8	21975	0	0	0
T9	1909	0	0	0
T10	2152	0	0	0
T13	0	57	0	0
T14	0	46	0	0
T35	0	3	0	0
T36	0	5	0	0
T39	0	1	0	0
T40	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24668266	160	0	0
T18	20096	20	0	0
T19	0	40	0	0
T20	0	40	0	0
T24	0	40	0	0
T25	0	20	0	0
T26	2567	0	0	0
T27	1244	0	0	0
T28	897	0	0	0
T29	41762	0	0	0
T30	415931	0	0	0
T31	407788	0	0	0
T32	651653	0	0	0
T33	6006	0	0	0
T34	233610	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24668266	4325	0	0
T1	4191	9	0	0
T2	4630	0	0	0
T3	1422	0	0	0
T4	14942	1	0	0
T5	5130	5	0	0
T6	3142	0	0	0
T7	47312	14	0	0
T8	21975	0	0	0
T9	1909	0	0	0
T10	2152	0	0	0
T13	0	57	0	0
T14	0	46	0	0
T35	0	3	0	0
T36	0	5	0	0
T39	0	1	0	0
T40	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24668266	1002933	0	0
T1	4191	200	0	0
T2	4630	0	0	0
T3	1422	0	0	0
T4	14942	0	0	0
T5	5130	535	0	0
T6	3142	0	0	0
T7	47312	1623	0	0
T8	21975	1999	0	0
T9	1909	0	0	0
T10	2152	26	0	0
T13	0	8614	0	0
T23	0	1468	0	0
T35	0	106	0	0
T36	0	98	0	0
T37	0	1424	0	0