Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	392244	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

153615

1

T1

3

T2

17

T3

11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	285091	1			T1	16		T2	30		T3	17
values[0x0]	130049	1			T1	3		T2	3		T3	13
values[0x1]	130719	1			T1	7		T2	7		T3	13

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	309975	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

235884

1

T1

10

T2

22

T3

14

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2443	1			T3	2		T8	1		T15	1
valid_sources[0x01]	1917	1			T2	1		T5	1		T15	1
valid_sources[0x02]	2676	1			T5	1		T26	1		T14	2
valid_sources[0x03]	1916	1			T26	1		T15	9		T16	1
valid_sources[0x04]	1754	1			T2	2		T8	1		T26	1
valid_sources[0x05]	5244	1			T8	2		T26	1		T15	5
valid_sources[0x06]	1921	1			T8	1		T37	3		T21	1
valid_sources[0x07]	2914	1			T7	1		T8	2		T37	5
valid_sources[0x08]	2315	1			T8	2		T15	6		T37	1
valid_sources[0x09]	1837	1			T5	2		T8	2		T15	5
valid_sources[0x0a]	2216	1			T26	1		T14	1		T15	7
valid_sources[0x0b]	2789	1			T5	1		T8	1		T26	1
valid_sources[0x0c]	1697	1			T5	1		T8	1		T15	6
valid_sources[0x0d]	2010	1			T2	3		T15	4		T37	2
valid_sources[0x0e]	1986	1			T5	1		T8	2		T26	1
valid_sources[0x0f]	1637	1			T8	2		T26	1		T37	4
valid_sources[0x10]	1512	1			T8	2		T15	3		T37	6
valid_sources[0x11]	2081	1			T8	3		T15	4		T37	8
valid_sources[0x12]	1633	1			T8	1		T26	1		T15	3
valid_sources[0x13]	3349	1			T5	1		T8	3		T14	1
valid_sources[0x14]	1598	1			T15	4		T37	4		T40	2
valid_sources[0x15]	2292	1			T26	1		T15	2		T37	12
valid_sources[0x16]	1859	1			T5	1		T8	1		T26	2
valid_sources[0x17]	2210	1			T15	3		T33	1		T16	1
valid_sources[0x18]	1781	1			T8	2		T26	1		T15	7
valid_sources[0x19]	1593	1			T4	5		T8	3		T15	4
valid_sources[0x1a]	2244	1			T2	2		T8	3		T35	1
valid_sources[0x1b]	1731	1			T5	1		T14	1		T37	4
valid_sources[0x1c]	1644	1			T4	4		T15	3		T33	1
valid_sources[0x1d]	1757	1			T1	3		T8	1		T26	2
valid_sources[0x1e]	3161	1			T5	1		T15	2		T37	1
valid_sources[0x1f]	2030	1			T5	4		T8	1		T15	3
valid_sources[0x20]	1885	1			T15	9		T37	3		T81	6
valid_sources[0x21]	1814	1			T5	1		T8	1		T14	1
valid_sources[0x22]	1657	1			T4	4		T5	2		T8	2
valid_sources[0x23]	1826	1			T8	4		T15	4		T37	5
valid_sources[0x24]	1828	1			T4	17		T5	1		T15	5
valid_sources[0x25]	1813	1			T15	6		T33	2		T16	1
valid_sources[0x26]	1908	1			T3	1		T8	1		T26	1
valid_sources[0x27]	1832	1			T5	1		T8	1		T15	2
valid_sources[0x28]	4200	1			T5	1		T8	3		T26	1
valid_sources[0x29]	1819	1			T8	1		T15	2		T31	3
valid_sources[0x2a]	1805	1			T3	2		T5	1		T8	3
valid_sources[0x2b]	1657	1			T5	1		T8	1		T14	1
valid_sources[0x2c]	1873	1			T26	1		T37	4		T31	2
valid_sources[0x2d]	2448	1			T5	3		T8	2		T15	5
valid_sources[0x2e]	1583	1			T5	1		T37	5		T148	1
valid_sources[0x2f]	1929	1			T6	1		T8	2		T41	1
valid_sources[0x30]	1598	1			T15	1		T16	1		T148	1
valid_sources[0x31]	1758	1			T26	1		T14	1		T15	4
valid_sources[0x32]	2663	1			T1	7		T8	1		T15	2
valid_sources[0x33]	1624	1			T26	1		T15	3		T37	1
valid_sources[0x34]	1727	1			T15	1		T37	2		T35	1
valid_sources[0x35]	1839	1			T8	1		T15	5		T37	5
valid_sources[0x36]	1890	1			T15	2		T16	2		T148	2
valid_sources[0x37]	1707	1			T8	1		T26	1		T15	3
valid_sources[0x38]	2084	1			T2	1		T8	1		T26	1
valid_sources[0x39]	1624	1			T8	5		T26	1		T15	5
valid_sources[0x3a]	1795	1			T5	5		T15	2		T37	8
valid_sources[0x3b]	2581	1			T26	1		T14	1		T15	3
valid_sources[0x3c]	2966	1			T8	1		T15	9		T37	1
valid_sources[0x3d]	1693	1			T14	1		T15	4		T37	1
valid_sources[0x3e]	2095	1			T8	1		T14	1		T15	4
valid_sources[0x3f]	1761	1			T15	2		T37	3		T21	1
valid_sources[0x40]	2716	1			T26	1		T15	1		T37	12
valid_sources[0x41]	1649	1			T5	1		T15	4		T33	2
valid_sources[0x42]	1798	1			T3	1		T8	1		T26	1
valid_sources[0x43]	1819	1			T8	2		T15	2		T37	3
valid_sources[0x44]	1962	1			T5	2		T15	2		T37	1
valid_sources[0x45]	1627	1			T5	3		T8	3		T14	2
valid_sources[0x46]	2436	1			T15	1		T17	1		T166	1
valid_sources[0x47]	1689	1			T8	1		T14	1		T15	5
valid_sources[0x48]	2309	1			T1	1		T8	1		T26	1
valid_sources[0x49]	2105	1			T15	1		T37	17		T35	1
valid_sources[0x4a]	3344	1			T2	1		T8	1		T26	1
valid_sources[0x4b]	2127	1			T5	1		T15	3		T37	1
valid_sources[0x4c]	1784	1			T26	1		T15	4		T37	5
valid_sources[0x4d]	1751	1			T3	1		T8	2		T15	5
valid_sources[0x4e]	2296	1			T8	2		T26	1		T15	3
valid_sources[0x4f]	1781	1			T8	3		T15	8		T37	5
valid_sources[0x50]	1914	1			T3	1		T5	1		T8	1
valid_sources[0x51]	1749	1			T3	1		T4	1		T8	1
valid_sources[0x52]	6739	1			T5	3		T8	1		T14	1
valid_sources[0x53]	1825	1			T5	2		T8	2		T15	4
valid_sources[0x54]	1788	1			T8	1		T15	4		T37	3
valid_sources[0x55]	1741	1			T15	10		T37	2		T148	1
valid_sources[0x56]	1622	1			T8	1		T14	1		T15	2
valid_sources[0x57]	1993	1			T2	1		T15	4		T37	3
valid_sources[0x58]	1913	1			T15	3		T37	9		T148	1
valid_sources[0x59]	1891	1			T8	1		T26	2		T37	8
valid_sources[0x5a]	1691	1			T5	2		T15	3		T37	5
valid_sources[0x5b]	2664	1			T5	1		T8	1		T26	1
valid_sources[0x5c]	3116	1			T5	2		T8	2		T37	2
valid_sources[0x5d]	2114	1			T1	5		T15	4		T33	1
valid_sources[0x5e]	1868	1			T5	1		T8	3		T26	1
valid_sources[0x5f]	1597	1			T3	1		T15	2		T41	7
valid_sources[0x60]	1651	1			T5	2		T8	1		T14	1
valid_sources[0x61]	1910	1			T3	1		T8	1		T15	6
valid_sources[0x62]	3083	1			T41	3		T37	1		T17	1
valid_sources[0x63]	2514	1			T26	1		T15	2		T21	1
valid_sources[0x64]	1774	1			T15	3		T37	3		T16	2
valid_sources[0x65]	1929	1			T5	1		T15	2		T16	1
valid_sources[0x66]	2643	1			T15	6		T41	3		T37	5
valid_sources[0x67]	3000	1			T8	1		T26	1		T15	4
valid_sources[0x68]	1616	1			T5	1		T15	1		T37	4
valid_sources[0x69]	2337	1			T2	1		T5	2		T8	1
valid_sources[0x6a]	2406	1			T5	1		T8	1		T26	1
valid_sources[0x6b]	1743	1			T8	1		T26	1		T15	5
valid_sources[0x6c]	1727	1			T2	1		T5	1		T26	2
valid_sources[0x6d]	1773	1			T8	1		T26	1		T15	2
valid_sources[0x6e]	2152	1			T15	1		T82	1		T17	3
valid_sources[0x6f]	2471	1			T2	1		T3	1		T26	1
valid_sources[0x70]	1672	1			T8	3		T39	1		T80	2
valid_sources[0x71]	2286	1			T1	1		T2	1		T3	1
valid_sources[0x72]	1976	1			T5	1		T15	2		T37	1
valid_sources[0x73]	1853	1			T5	1		T8	1		T15	5
valid_sources[0x74]	1838	1			T26	1		T15	1		T41	15
valid_sources[0x75]	2722	1			T15	2		T37	2		T33	2
valid_sources[0x76]	1670	1			T3	1		T8	3		T15	1
valid_sources[0x77]	3143	1			T8	1		T15	4		T37	2
valid_sources[0x78]	1575	1			T26	1		T14	1		T41	3
valid_sources[0x79]	2108	1			T15	4		T37	1		T38	283
valid_sources[0x7a]	1691	1			T2	1		T5	2		T8	2
valid_sources[0x7b]	1416	1			T8	1		T26	1		T41	2
valid_sources[0x7c]	2504	1			T8	4		T15	4		T39	3
valid_sources[0x7d]	6107	1			T9	229		T26	1		T14	2
valid_sources[0x7e]	1911	1			T5	2		T14	1		T15	5
valid_sources[0x7f]	6782	1			T8	3		T14	1		T15	2
valid_sources[0x80]	2625	1			T3	2		T5	1		T8	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

76830

1

T1

2

T2

14

T3

5

values[0x0]

all_enables

biggest_size

49293

1

T1

1

T3

4

T4

2

values[0x1]

all_enables

biggest_size

27492

1

T2

3

T3

2

T5

4