Module Definition
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Module : prim_mubi4_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_cdc.u_sync_rom_ctrl 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_cdc.u_sync_rom_ctrl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.u_mubi_xor 100.00 100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage 100.00 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_mubi4_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00

95 // hence this mux can be implemented behaviorally. 96 4/4 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  97 end 98 99 // Note regarding SVAs below: 100 // 101 // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after 102 // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed" 103 // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page 104 // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni 105 // on the active clock edge. This causes the assertion to evaluate although the reset was actually 106 // 0 when entering this simulation cycle. 107 // 108 // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may 109 // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly 110 // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock 111 // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make 112 // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no 113 // sampling mismatches. 114 `ifdef INC_ASSERT 115 mubi4_t mubi_in_sva_q; 116 always_ff @(posedge clk_i) begin 117 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  118 end 119 `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}}) 120 `ASSERT(OutputDelay_A, 121 rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}}) 122 `endif 123 end else begin : gen_no_stable_chks 124 assign mubi = mubi_sync; 125 `ifdef INC_ASSERT 126 mubi4_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 mubi_in_sva_q <= mubi_i; 129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi4_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi4False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi4Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 1/1 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Cond Coverage for Module : prim_mubi4_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : prim_mubi4_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00


96 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


96 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k]; Warning: the following expressions can not be annotated -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


96 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k]; Warning: the following expressions can not be annotated -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


96 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k]; Warning: the following expressions can not be annotated -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_mubi4_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 951 951 0 0
OutputsKnown_A 15003033 14586352 0 0
gen_flops.gen_stable_chks.OutputDelay_A 15003033 14569531 0 2553
gen_flops.gen_stable_chks.OutputIfUnstable_A 15003033 24503 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 951 951 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 15003033 14586352 0 0
T1 1102 1030 0 0
T2 2162 2104 0 0
T3 1870 1775 0 0
T4 2588 2492 0 0
T5 2132 2049 0 0
T6 699 561 0 0
T7 1673 1202 0 0
T8 3555 3475 0 0
T9 6165 6103 0 0
T10 3633 3183 0 0

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 15003033 14569531 0 2553
T1 1102 1027 0 3
T2 2162 2101 0 3
T3 1870 1772 0 3
T4 2588 2489 0 3
T5 2132 2046 0 3
T6 699 555 0 3
T7 1673 1184 0 3
T8 3555 3472 0 3
T9 6165 6100 0 3
T10 3633 3168 0 3

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 15003033 24503 0 0
T1 1102 1 0 0
T2 2162 1 0 0
T3 1870 1 0 0
T4 2588 1 0 0
T5 2132 1 0 0
T6 699 2 0 0
T7 1673 6 0 0
T8 3555 1 0 0
T9 6165 50 0 0
T10 3633 5 0 0

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