Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

32                      
33         1/1            always_comb reset_or_disable = !rst_slow_ni || disable_sva;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T41,T45,T80

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	18688288	4952	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	18688288	219347	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	18688288	7633933	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	18688288	219355	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	18688288	4952	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	18688288	219347	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	18688288	7633933	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	18688288	219355	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18688288	4952	0	0
T4	2588	1	0	0
T5	2132	0	0	0
T6	699	0	0	0
T7	1673	0	0	0
T8	3555	0	0	0
T9	6165	5	0	0
T10	3633	0	0	0
T11	9698	0	0	0
T13	3432	0	0	0
T15	0	21	0	0
T26	4951	0	0	0
T31	0	1	0	0
T37	0	20	0	0
T38	0	5	0	0
T41	0	1	0	0
T45	0	2	0	0
T81	0	1	0	0
T82	0	1	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18688288	219347	0	0
T4	2588	15	0	0
T5	2132	0	0	0
T6	699	0	0	0
T7	1673	0	0	0
T8	3555	0	0	0
T9	6165	120	0	0
T10	3633	0	0	0
T11	9698	0	0	0
T13	3432	0	0	0
T15	0	676	0	0
T26	4951	0	0	0
T31	0	12	0	0
T37	0	1086	0	0
T38	0	287	0	0
T41	0	205	0	0
T45	0	453	0	0
T81	0	12	0	0
T82	0	10	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18688288	7633933	0	0
T2	2162	1298	0	0
T3	1870	1146	0	0
T4	2588	1652	0	0
T5	2132	183	0	0
T6	699	0	0	0
T7	1673	0	0	0
T8	3555	0	0	0
T9	6165	2039	0	0
T10	3633	0	0	0
T15	0	15666	0	0
T26	4951	1718	0	0
T31	0	825	0	0
T37	0	25499	0	0
T41	0	748	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18688288	219355	0	0
T4	2588	15	0	0
T5	2132	0	0	0
T6	699	0	0	0
T7	1673	0	0	0
T8	3555	0	0	0
T9	6165	120	0	0
T10	3633	0	0	0
T11	9698	0	0	0
T13	3432	0	0	0
T15	0	676	0	0
T26	4951	0	0	0
T31	0	12	0	0
T37	0	1086	0	0
T38	0	287	0	0
T41	0	205	0	0
T45	0	453	0	0
T81	0	12	0	0
T82	0	10	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18688288	4952	0	0
T4	2588	1	0	0
T5	2132	0	0	0
T6	699	0	0	0
T7	1673	0	0	0
T8	3555	0	0	0
T9	6165	5	0	0
T10	3633	0	0	0
T11	9698	0	0	0
T13	3432	0	0	0
T15	0	21	0	0
T26	4951	0	0	0
T31	0	1	0	0
T37	0	20	0	0
T38	0	5	0	0
T41	0	1	0	0
T45	0	2	0	0
T81	0	1	0	0
T82	0	1	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18688288	219347	0	0
T4	2588	15	0	0
T5	2132	0	0	0
T6	699	0	0	0
T7	1673	0	0	0
T8	3555	0	0	0
T9	6165	120	0	0
T10	3633	0	0	0
T11	9698	0	0	0
T13	3432	0	0	0
T15	0	676	0	0
T26	4951	0	0	0
T31	0	12	0	0
T37	0	1086	0	0
T38	0	287	0	0
T41	0	205	0	0
T45	0	453	0	0
T81	0	12	0	0
T82	0	10	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18688288	7633933	0	0
T2	2162	1298	0	0
T3	1870	1146	0	0
T4	2588	1652	0	0
T5	2132	183	0	0
T6	699	0	0	0
T7	1673	0	0	0
T8	3555	0	0	0
T9	6165	2039	0	0
T10	3633	0	0	0
T15	0	15666	0	0
T26	4951	1718	0	0
T31	0	825	0	0
T37	0	25499	0	0
T41	0	748	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18688288	219355	0	0
T4	2588	15	0	0
T5	2132	0	0	0
T6	699	0	0	0
T7	1673	0	0	0
T8	3555	0	0	0
T9	6165	120	0	0
T10	3633	0	0	0
T11	9698	0	0	0
T13	3432	0	0	0
T15	0	676	0	0
T26	4951	0	0	0
T31	0	12	0	0
T37	0	1086	0	0
T38	0	287	0	0
T41	0	205	0	0
T45	0	453	0	0
T81	0	12	0	0
T82	0	10	0	0