Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	19192046	15033	0	0
intr_enable_rd_A	19192046	31322	0	0
reset_en_rd_A	19192046	844	0	0
reset_en_regwen_rd_A	19192046	607	0	0
wake_info_capture_dis_rd_A	19192046	724	0	0
wakeup_en_rd_A	19192046	1410	0	0
wakeup_en_regwen_rd_A	19192046	648	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19192046	15033	0	0
T23	176727	5	0	0
T24	0	38	0	0
T25	0	15	0	0
T50	0	26	0	0
T85	0	65	0	0
T86	0	31	0	0
T87	0	2	0	0
T102	0	3	0	0
T137	0	37	0	0
T138	0	26	0	0
T139	57017	0	0	0
T140	542	0	0	0
T141	1558	0	0	0
T142	2819	0	0	0
T143	2948	0	0	0
T144	5254	0	0	0
T145	2462	0	0	0
T146	923	0	0	0
T147	3825	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19192046	31322	0	0
T1	1102	6	0	0
T2	2162	0	0	0
T3	1870	2	0	0
T4	2588	0	0	0
T5	2132	0	0	0
T6	699	0	0	0
T7	1673	0	0	0
T8	3555	0	0	0
T9	6165	22	0	0
T10	3633	0	0	0
T14	0	4	0	0
T15	0	193	0	0
T16	0	50	0	0
T33	0	31	0	0
T35	0	6	0	0
T36	0	46	0	0
T148	0	98	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19192046	844	0	0
T23	176727	3	0	0
T24	0	20	0	0
T50	0	9	0	0
T87	0	6	0	0
T102	0	2	0	0
T139	57017	0	0	0
T140	542	0	0	0
T141	1558	0	0	0
T142	2819	0	0	0
T143	2948	0	0	0
T144	5254	0	0	0
T145	2462	0	0	0
T146	923	0	0	0
T147	3825	0	0	0
T149	0	1	0	0
T150	0	22	0	0
T151	0	17	0	0
T152	0	14	0	0
T153	0	16	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19192046	607	0	0
T23	176727	6	0	0
T24	0	10	0	0
T50	0	27	0	0
T87	0	5	0	0
T102	0	2	0	0
T139	57017	0	0	0
T140	542	0	0	0
T141	1558	0	0	0
T142	2819	0	0	0
T143	2948	0	0	0
T144	5254	0	0	0
T145	2462	0	0	0
T146	923	0	0	0
T147	3825	0	0	0
T149	0	7	0	0
T150	0	15	0	0
T151	0	14	0	0
T152	0	15	0	0
T153	0	30	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19192046	724	0	0
T23	176727	6	0	0
T24	0	7	0	0
T50	0	24	0	0
T87	0	7	0	0
T102	0	10	0	0
T139	57017	0	0	0
T140	542	0	0	0
T141	1558	0	0	0
T142	2819	0	0	0
T143	2948	0	0	0
T144	5254	0	0	0
T145	2462	0	0	0
T146	923	0	0	0
T147	3825	0	0	0
T149	0	8	0	0
T150	0	17	0	0
T151	0	3	0	0
T152	0	17	0	0
T153	0	17	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19192046	1410	0	0
T23	176727	13	0	0
T24	0	1	0	0
T50	0	25	0	0
T87	0	10	0	0
T102	0	7	0	0
T139	57017	0	0	0
T140	542	0	0	0
T141	1558	0	0	0
T142	2819	0	0	0
T143	2948	0	0	0
T144	5254	0	0	0
T145	2462	0	0	0
T146	923	0	0	0
T147	3825	0	0	0
T150	0	12	0	0
T151	0	16	0	0
T152	0	18	0	0
T153	0	12	0	0
T154	0	2	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19192046	648	0	0
T23	176727	3	0	0
T24	0	7	0	0
T50	0	16	0	0
T87	0	4	0	0
T102	0	8	0	0
T139	57017	0	0	0
T140	542	0	0	0
T141	1558	0	0	0
T142	2819	0	0	0
T143	2948	0	0	0
T144	5254	0	0	0
T145	2462	0	0	0
T146	923	0	0	0
T147	3825	0	0	0
T149	0	4	0	0
T150	0	6	0	0
T151	0	17	0	0
T152	0	26	0	0
T153	0	19	0	0