Unified Coverage Report :: Module

Module : prim_generic_buf

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sw_req_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_reg.u_prim_reg_we_check.u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_cdc.u_sync_rom_ctrl.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_cdc.u_sync_rom_ctrl.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_cdc.u_sync_rom_ctrl.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_cdc.u_sync_rom_ctrl.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_lc_sync_dft_en.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_lc_sync_dft_en.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_lc_sync_dft_en.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_lc_sync_dft_en.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00

Module Instance : tb.dut.u_sw_req_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sw_req_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_prim_reg_we_check.u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_prim_lc_sync_dft_en.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_prim_lc_sync_dft_en.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_prim_lc_sync_dft_en.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_prim_lc_sync_dft_en.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_buf

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T1 T2 T3 
16         1/1            assign out_o = ~inv;
           Tests:       T1 T2 T3

Line Coverage for Instance : tb.dut.u_sw_req_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T1 T8 T13 
16         1/1            assign out_o = ~inv;
           Tests:       T1 T8 T13

Line Coverage for Instance : tb.dut.u_reg.u_prim_reg_we_check.u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T1 T2 T3 
16         1/1            assign out_o = ~inv;
           Tests:       T1 T2 T3

Line Coverage for Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T1 T2 T3 
16         1/1            assign out_o = ~inv;
           Tests:       T1 T2 T3

Line Coverage for Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T1 T2 T3 
16         1/1            assign out_o = ~inv;
           Tests:       T1 T2 T3

Line Coverage for Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T1 T2 T3 
16         1/1            assign out_o = ~inv;
           Tests:       T1 T2 T3

Line Coverage for Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T1 T2 T3 
16         1/1            assign out_o = ~inv;
           Tests:       T1 T2 T3

Line Coverage for Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T1 T2 T3 
16         1/1            assign out_o = ~inv;
           Tests:       T1 T2 T3

Line Coverage for Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T1 T2 T3 
16         1/1            assign out_o = ~inv;
           Tests:       T1 T2 T3

Line Coverage for Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T1 T2 T3 
16         1/1            assign out_o = ~inv;
           Tests:       T1 T2 T3

Line Coverage for Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T1 T2 T3 
16         1/1            assign out_o = ~inv;
           Tests:       T1 T2 T3

Line Coverage for Instance : tb.dut.u_prim_lc_sync_dft_en.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T1 T2 T3 
16         1/1            assign out_o = ~inv;
           Tests:       T1 T2 T3

Line Coverage for Instance : tb.dut.u_prim_lc_sync_dft_en.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T1 T2 T3 
16         1/1            assign out_o = ~inv;
           Tests:       T1 T2 T3

Line Coverage for Instance : tb.dut.u_prim_lc_sync_dft_en.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T1 T2 T3 
16         1/1            assign out_o = ~inv;
           Tests:       T1 T2 T3

Line Coverage for Instance : tb.dut.u_prim_lc_sync_dft_en.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T1 T2 T3 
16         1/1            assign out_o = ~inv;
           Tests:       T1 T2 T3

Line Coverage for Instance : tb.dut.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T1 T2 T3 
16         1/1            assign out_o = ~inv;
           Tests:       T1 T2 T3

Line Coverage for Instance : tb.dut.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T1 T2 T3 
16         1/1            assign out_o = ~inv;
           Tests:       T1 T2 T3

Line Coverage for Instance : tb.dut.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T1 T2 T3 
16         1/1            assign out_o = ~inv;
           Tests:       T1 T2 T3

Line Coverage for Instance : tb.dut.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T1 T2 T3 
16         1/1            assign out_o = ~inv;
           Tests:       T1 T2 T3