Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	56064864	110990	0	0
StatusRise_A	56064864	124332	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56064864	110990	0	0
T1	3306	6	0	0
T2	6486	3	0	0
T3	5610	7	0	0
T4	7764	6	0	0
T5	6396	15	0	0
T6	2097	3	0	0
T7	5019	0	0	0
T8	10665	3	0	0
T9	18495	68	0	0
T10	10899	0	0	0
T11	0	12	0	0
T26	0	19	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56064864	124332	0	0
T1	3306	9	0	0
T2	6486	6	0	0
T3	5610	10	0	0
T4	7764	9	0	0
T5	6396	18	0	0
T6	2097	9	0	0
T7	5019	18	0	0
T8	10665	6	0	0
T9	18495	71	0	0
T10	10899	15	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	18688288	41282	0	0
StatusRise_A	18688288	46069	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18688288	41282	0	0
T1	1102	2	0	0
T2	2162	1	0	0
T3	1870	3	0	0
T4	2588	2	0	0
T5	2132	5	0	0
T6	699	1	0	0
T7	1673	0	0	0
T8	3555	1	0	0
T9	6165	25	0	0
T10	3633	0	0	0
T11	0	4	0	0
T26	0	7	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18688288	46069	0	0
T1	1102	3	0	0
T2	2162	2	0	0
T3	1870	4	0	0
T4	2588	3	0	0
T5	2132	6	0	0
T6	699	3	0	0
T7	1673	6	0	0
T8	3555	2	0	0
T9	6165	26	0	0
T10	3633	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	18688288	41285	0	0
StatusRise_A	18688288	46070	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18688288	41285	0	0
T1	1102	2	0	0
T2	2162	1	0	0
T3	1870	3	0	0
T4	2588	2	0	0
T5	2132	5	0	0
T6	699	1	0	0
T7	1673	0	0	0
T8	3555	1	0	0
T9	6165	25	0	0
T10	3633	0	0	0
T11	0	4	0	0
T26	0	7	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18688288	46070	0	0
T1	1102	3	0	0
T2	2162	2	0	0
T3	1870	4	0	0
T4	2588	3	0	0
T5	2132	6	0	0
T6	699	3	0	0
T7	1673	6	0	0
T8	3555	2	0	0
T9	6165	26	0	0
T10	3633	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	18688288	28423	0	0
StatusRise_A	18688288	32193	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18688288	28423	0	0
T1	1102	2	0	0
T2	2162	1	0	0
T3	1870	1	0	0
T4	2588	2	0	0
T5	2132	5	0	0
T6	699	1	0	0
T7	1673	0	0	0
T8	3555	1	0	0
T9	6165	18	0	0
T10	3633	0	0	0
T11	0	4	0	0
T26	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18688288	32193	0	0
T1	1102	3	0	0
T2	2162	2	0	0
T3	1870	2	0	0
T4	2588	3	0	0
T5	2132	6	0	0
T6	699	3	0	0
T7	1673	6	0	0
T8	3555	2	0	0
T9	6165	19	0	0
T10	3633	5	0	0