Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

41                      
42         1/1            always_comb reset_or_disable = !rst_ni || disable_sva;
           Tests:       T1 T2 T3 
43         1/1            always_comb esc_reset_or_disable = !rst_esc_ni || disable_sva;
           Tests:       T1 T2 T3 
44         1/1            always_comb slow_reset_or_disable = !rst_slow_ni || disable_sva;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	18688853	10380	0	0
EscTimeoutStoppedByClReset_A	18688288	2634432	0	0
EscTimeoutTriggersReset_A	3743359	428	0	0
RomAllowActiveState_A	18688288	45668	0	0
RomAllowCheckGoodState_A	18688288	45720	0	0
RomBlockActiveState_A	18688288	27093	0	0
RomBlockCheckGoodState_A	18688288	391263	0	0
RomIntgChkDisFalse_A	18688288	18153015	0	0
RomIntgChkDisTrue_A	18688288	114413	0	0
RstreqChkEsctimeout_A	18688288	3355	0	0
RstreqChkFsmterm_A	18688288	140	0	0
RstreqChkGlbesc_A	18688288	3355	0	0
RstreqChkMainpd_A	18688288	814568	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18688853	10380	0	0
T6	700	3	0	0
T7	1674	0	0	0
T8	3556	0	0	0
T9	6166	0	0	0
T10	3634	0	0	0
T11	9699	145	0	0
T12	0	321	0	0
T13	3433	0	0	0
T14	5091	0	0	0
T15	35680	0	0	0
T26	4951	0	0	0
T42	0	159	0	0
T96	0	190	0	0
T145	0	21	0	0
T155	0	289	0	0
T156	0	418	0	0
T157	0	373	0	0
T158	0	275	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18688288	2634432	0	0
T1	1102	35	0	0
T2	2162	40	0	0
T3	1870	101	0	0
T4	2588	15	0	0
T5	2132	1	0	0
T6	699	31	0	0
T7	1673	28	0	0
T8	3555	14	0	0
T9	6165	847	0	0
T10	3633	18	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3743359	428	0	0
T6	325	7	0	0
T7	2440	0	0	0
T8	1013	0	0	0
T9	2434	0	0	0
T10	339	0	0	0
T11	240	4	0	0
T12	0	4	0	0
T13	1154	0	0	0
T14	378	0	0	0
T15	7240	0	0	0
T26	967	0	0	0
T34	0	3	0	0
T42	0	4	0	0
T145	0	2	0	0
T155	0	4	0	0
T156	0	5	0	0
T159	0	2	0	0
T160	0	2	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18688288	45668	0	0
T1	1102	3	0	0
T2	2162	2	0	0
T3	1870	4	0	0
T4	2588	3	0	0
T5	2132	6	0	0
T6	699	3	0	0
T7	1673	6	0	0
T8	3555	2	0	0
T9	6165	26	0	0
T10	3633	5	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18688288	45720	0	0
T1	1102	3	0	0
T2	2162	2	0	0
T3	1870	4	0	0
T4	2588	3	0	0
T5	2132	6	0	0
T6	699	3	0	0
T7	1673	6	0	0
T8	3555	2	0	0
T9	6165	26	0	0
T10	3633	5	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18688288	27093	0	0
T12	10492	0	0	0
T14	5090	844	0	0
T15	35679	0	0	0
T20	22363	0	0	0
T28	0	527	0	0
T31	1063	0	0	0
T32	2568	0	0	0
T33	4472	0	0	0
T34	2356	0	0	0
T37	53541	0	0	0
T41	3074	0	0	0
T47	0	292	0	0
T95	0	898	0	0
T144	0	874	0	0
T161	0	7	0	0
T162	0	5	0	0
T163	0	3	0	0
T164	0	14	0	0
T165	0	176	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18688288	391263	0	0
T9	6165	297	0	0
T10	3633	0	0	0
T11	9698	0	0	0
T13	3432	0	0	0
T14	5090	908	0	0
T15	35679	2257	0	0
T20	22363	0	0	0
T26	4951	0	0	0
T28	0	309	0	0
T37	53541	4161	0	0
T38	0	343	0	0
T41	3074	0	0	0
T62	0	1341	0	0
T80	0	2298	0	0
T166	0	161	0	0
T167	0	4011	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18688288	18153015	0	0
T1	1102	1030	0	0
T2	2162	2104	0	0
T3	1870	1775	0	0
T4	2588	2492	0	0
T5	2132	2049	0	0
T6	699	561	0	0
T7	1673	1202	0	0
T8	3555	3475	0	0
T9	6165	6103	0	0
T10	3633	3183	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18688288	114413	0	0
T12	10492	0	0	0
T14	5090	263	0	0
T15	35679	935	0	0
T20	22363	0	0	0
T28	0	92	0	0
T31	1063	0	0	0
T32	2568	0	0	0
T33	4472	0	0	0
T34	2356	0	0	0
T37	53541	0	0	0
T41	3074	0	0	0
T47	0	68	0	0
T91	0	203	0	0
T161	0	525	0	0
T162	0	169	0	0
T164	0	25	0	0
T167	0	33372	0	0
T168	0	3558	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18688288	3355	0	0
T1	1102	1	0	0
T2	2162	0	0	0
T3	1870	0	0	0
T4	2588	0	0	0
T5	2132	0	0	0
T6	699	1	0	0
T7	1673	5	0	0
T8	3555	0	0	0
T9	6165	0	0	0
T10	3633	0	0	0
T11	0	2	0	0
T12	0	2	0	0
T13	0	6	0	0
T14	0	4	0	0
T20	0	10	0	0
T32	0	7	0	0
T34	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18688288	140	0	0
T12	10492	0	0	0
T18	1158	0	0	0
T20	22363	20	0	0
T21	43828	40	0	0
T22	0	40	0	0
T29	0	20	0	0
T30	0	20	0	0
T31	1063	0	0	0
T32	2568	0	0	0
T33	4472	0	0	0
T34	2356	0	0	0
T35	3358	0	0	0
T36	5771	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18688288	3355	0	0
T1	1102	1	0	0
T2	2162	0	0	0
T3	1870	0	0	0
T4	2588	0	0	0
T5	2132	0	0	0
T6	699	1	0	0
T7	1673	5	0	0
T8	3555	0	0	0
T9	6165	0	0	0
T10	3633	0	0	0
T11	0	2	0	0
T12	0	2	0	0
T13	0	6	0	0
T14	0	4	0	0
T20	0	10	0	0
T32	0	7	0	0
T34	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18688288	814568	0	0
T9	6165	439	0	0
T10	3633	17	0	0
T11	9698	0	0	0
T13	3432	140	0	0
T14	5090	1272	0	0
T15	35679	2328	0	0
T18	0	21	0	0
T20	22363	0	0	0
T26	4951	0	0	0
T28	0	532	0	0
T32	0	77	0	0
T37	53541	4098	0	0
T38	0	949	0	0
T41	3074	0	0	0