Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	377354	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

148567

1

T1

8

T2

3

T3

62

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	274063	1			T1	17		T2	13		T3	125
values[0x0]	125709	1			T1	5		T2	2		T3	62
values[0x1]	126149	1			T1	5		T2	4		T3	76

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	298738	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

227183

1

T1

13

T2

6

T3

104

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1715	1			T3	1		T4	3		T6	6
valid_sources[0x01]	1862	1			T4	1		T9	2		T42	1
valid_sources[0x02]	2400	1			T4	1		T6	1		T8	2
valid_sources[0x03]	1802	1			T3	2		T4	1		T7	2
valid_sources[0x04]	1723	1			T4	1		T9	2		T14	5
valid_sources[0x05]	1838	1			T3	2		T4	1		T7	1
valid_sources[0x06]	1766	1			T4	1		T9	1		T42	1
valid_sources[0x07]	1872	1			T4	2		T6	3		T8	2
valid_sources[0x08]	2143	1			T4	1		T8	1		T9	1
valid_sources[0x09]	2152	1			T7	6		T42	1		T14	5
valid_sources[0x0a]	2583	1			T4	4		T7	2		T9	1
valid_sources[0x0b]	1827	1			T1	4		T6	10		T14	4
valid_sources[0x0c]	1721	1			T4	2		T6	2		T7	3
valid_sources[0x0d]	2616	1			T3	2		T6	3		T42	1
valid_sources[0x0e]	1490	1			T3	3		T6	1		T7	2
valid_sources[0x0f]	1597	1			T4	2		T9	1		T42	1
valid_sources[0x10]	2112	1			T3	4		T4	1		T8	1
valid_sources[0x11]	1653	1			T9	1		T14	1		T39	1
valid_sources[0x12]	1819	1			T4	3		T9	1		T42	1
valid_sources[0x13]	1647	1			T4	1		T6	4		T9	1
valid_sources[0x14]	1535	1			T1	1		T3	2		T4	2
valid_sources[0x15]	1895	1			T9	1		T45	1		T14	7
valid_sources[0x16]	1799	1			T3	4		T4	3		T8	2
valid_sources[0x17]	1747	1			T8	1		T9	1		T14	2
valid_sources[0x18]	1394	1			T9	2		T14	6		T15	4
valid_sources[0x19]	1582	1			T9	1		T42	1		T15	2
valid_sources[0x1a]	1768	1			T1	1		T4	1		T9	1
valid_sources[0x1b]	1786	1			T7	2		T8	2		T9	3
valid_sources[0x1c]	1829	1			T3	1		T4	1		T8	2
valid_sources[0x1d]	1853	1			T3	2		T4	1		T6	1
valid_sources[0x1e]	1847	1			T2	4		T3	1		T4	1
valid_sources[0x1f]	1693	1			T7	1		T8	2		T9	3
valid_sources[0x20]	1536	1			T3	8		T4	1		T14	3
valid_sources[0x21]	1693	1			T14	3		T39	2		T48	4
valid_sources[0x22]	1963	1			T1	1		T3	4		T4	1
valid_sources[0x23]	1630	1			T4	1		T9	1		T14	5
valid_sources[0x24]	2338	1			T4	1		T7	3		T9	1
valid_sources[0x25]	1739	1			T7	2		T9	4		T42	2
valid_sources[0x26]	1794	1			T4	2		T42	4		T14	3
valid_sources[0x27]	2257	1			T3	1		T4	1		T42	1
valid_sources[0x28]	3298	1			T8	1		T9	1		T14	4
valid_sources[0x29]	1928	1			T42	2		T14	4		T39	3
valid_sources[0x2a]	2070	1			T1	3		T3	3		T6	15
valid_sources[0x2b]	1480	1			T3	3		T4	2		T6	2
valid_sources[0x2c]	1932	1			T4	2		T14	2		T39	3
valid_sources[0x2d]	2214	1			T4	1		T42	4		T45	1
valid_sources[0x2e]	2690	1			T3	1		T9	1		T42	1
valid_sources[0x2f]	3104	1			T4	1		T7	1		T9	1
valid_sources[0x30]	1626	1			T4	3		T9	1		T42	2
valid_sources[0x31]	1709	1			T4	2		T9	1		T11	1
valid_sources[0x32]	1687	1			T1	1		T3	3		T8	1
valid_sources[0x33]	1751	1			T3	3		T8	1		T9	1
valid_sources[0x34]	2642	1			T4	3		T8	2		T9	4
valid_sources[0x35]	1866	1			T3	3		T4	1		T14	2
valid_sources[0x36]	2191	1			T3	2		T4	1		T6	3
valid_sources[0x37]	3025	1			T1	1		T4	1		T9	2
valid_sources[0x38]	1958	1			T3	1		T4	1		T8	1
valid_sources[0x39]	2834	1			T9	1		T14	3		T38	4
valid_sources[0x3a]	2022	1			T3	1		T4	4		T5	1
valid_sources[0x3b]	1759	1			T4	1		T7	9		T8	2
valid_sources[0x3c]	1543	1			T3	3		T4	3		T42	1
valid_sources[0x3d]	1571	1			T3	2		T4	1		T7	29
valid_sources[0x3e]	1751	1			T3	1		T4	2		T9	2
valid_sources[0x3f]	1542	1			T8	6		T9	2		T42	2
valid_sources[0x40]	2670	1			T3	1		T4	1		T7	2
valid_sources[0x41]	1643	1			T3	1		T4	1		T6	3
valid_sources[0x42]	2531	1			T6	2		T14	4		T15	3
valid_sources[0x43]	1714	1			T3	1		T4	1		T9	3
valid_sources[0x44]	2895	1			T4	1		T6	6		T8	2
valid_sources[0x45]	2450	1			T9	1		T42	2		T14	4
valid_sources[0x46]	1813	1			T3	2		T6	5		T9	1
valid_sources[0x47]	1952	1			T8	1		T42	5		T14	4
valid_sources[0x48]	1838	1			T4	2		T6	4		T8	1
valid_sources[0x49]	1988	1			T3	4		T4	1		T7	4
valid_sources[0x4a]	2225	1			T7	3		T9	3		T42	1
valid_sources[0x4b]	1992	1			T3	1		T6	3		T8	3
valid_sources[0x4c]	1761	1			T3	1		T7	3		T8	1
valid_sources[0x4d]	1816	1			T3	2		T4	1		T9	3
valid_sources[0x4e]	2652	1			T4	1		T8	4		T9	3
valid_sources[0x4f]	4279	1			T4	1		T6	1		T14	8
valid_sources[0x50]	1921	1			T3	2		T7	3		T14	4
valid_sources[0x51]	2721	1			T3	2		T8	1		T9	2
valid_sources[0x52]	1683	1			T1	3		T3	6		T4	1
valid_sources[0x53]	1719	1			T4	1		T8	1		T14	5
valid_sources[0x54]	2019	1			T6	1		T9	1		T42	5
valid_sources[0x55]	2000	1			T4	1		T8	2		T9	1
valid_sources[0x56]	1676	1			T3	1		T14	5		T15	1
valid_sources[0x57]	2681	1			T3	1		T7	6		T42	1
valid_sources[0x58]	1744	1			T3	1		T7	5		T9	1
valid_sources[0x59]	1647	1			T3	6		T4	1		T42	1
valid_sources[0x5a]	1614	1			T3	5		T6	2		T14	3
valid_sources[0x5b]	1661	1			T3	2		T6	9		T8	1
valid_sources[0x5c]	1893	1			T4	1		T6	6		T7	1
valid_sources[0x5d]	2110	1			T3	3		T9	1		T42	1
valid_sources[0x5e]	1988	1			T3	3		T6	9		T9	2
valid_sources[0x5f]	1741	1			T1	1		T3	1		T4	1
valid_sources[0x60]	1881	1			T3	2		T6	3		T8	4
valid_sources[0x61]	1737	1			T3	2		T4	1		T7	6
valid_sources[0x62]	1897	1			T3	4		T4	1		T9	1
valid_sources[0x63]	1733	1			T1	1		T3	1		T4	1
valid_sources[0x64]	1857	1			T4	1		T6	2		T7	1
valid_sources[0x65]	2450	1			T4	1		T9	4		T39	5
valid_sources[0x66]	1824	1			T3	3		T4	1		T6	1
valid_sources[0x67]	1830	1			T3	1		T8	2		T14	3
valid_sources[0x68]	1733	1			T4	3		T6	7		T8	1
valid_sources[0x69]	3680	1			T3	1		T9	4		T14	2
valid_sources[0x6a]	2092	1			T3	1		T9	1		T42	1
valid_sources[0x6b]	1645	1			T3	2		T6	5		T8	2
valid_sources[0x6c]	1593	1			T4	2		T8	2		T9	1
valid_sources[0x6d]	1944	1			T3	2		T6	2		T8	2
valid_sources[0x6e]	1828	1			T4	1		T6	4		T8	2
valid_sources[0x6f]	1704	1			T1	2		T3	1		T4	1
valid_sources[0x70]	2667	1			T9	1		T42	1		T14	3
valid_sources[0x71]	1926	1			T3	3		T42	1		T14	3
valid_sources[0x72]	1582	1			T3	1		T4	1		T7	4
valid_sources[0x73]	1892	1			T4	3		T42	2		T14	5
valid_sources[0x74]	1920	1			T4	2		T8	1		T42	1
valid_sources[0x75]	2324	1			T6	4		T9	3		T14	6
valid_sources[0x76]	1732	1			T2	2		T3	3		T4	3
valid_sources[0x77]	1929	1			T4	1		T8	5		T9	1
valid_sources[0x78]	1697	1			T3	1		T8	1		T14	5
valid_sources[0x79]	1859	1			T4	3		T14	3		T15	3
valid_sources[0x7a]	2005	1			T3	2		T4	1		T7	8
valid_sources[0x7b]	2028	1			T7	4		T9	2		T14	2
valid_sources[0x7c]	3302	1			T3	5		T42	1		T14	5
valid_sources[0x7d]	2583	1			T3	1		T7	1		T8	6
valid_sources[0x7e]	1984	1			T3	2		T4	1		T6	2
valid_sources[0x7f]	1949	1			T4	1		T6	8		T14	2
valid_sources[0x80]	1843	1			T14	4		T15	2		T39	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

74122

1

T1

7

T2

3

T3

26

values[0x0]

all_enables

biggest_size

47816

1

T3

26

T4

23

T6

17

values[0x1]

all_enables

biggest_size

26629

1

T1

1

T3

10

T4

12