SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 32053 | 1 | T14 | 290 | T39 | 406 | T40 | 430 | ||||
others[1] | 32381 | 1 | T14 | 293 | T39 | 406 | T40 | 410 | ||||
others[2] | 32367 | 1 | T14 | 320 | T39 | 406 | T40 | 401 | ||||
others[3] | 53529 | 1 | T14 | 504 | T39 | 651 | T40 | 637 | ||||
false | 14545 | 1 | T9 | 36 | T13 | 4 | T14 | 50 | ||||
true | 23017 | 1 | T1 | 1 | T2 | 1 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 32391 | 1 | T13 | 1 | T14 | 299 | T39 | 434 | ||||
others[1] | 32135 | 1 | T13 | 1 | T14 | 296 | T39 | 397 | ||||
others[2] | 32289 | 1 | T14 | 292 | T39 | 410 | T40 | 386 | ||||
others[3] | 53681 | 1 | T14 | 504 | T39 | 618 | T40 | 656 | ||||
false | 9689 | 1 | T9 | 18 | T13 | 2 | T14 | 50 | ||||
true | 18213 | 1 | T1 | 1 | T2 | 1 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 529 | 1 | T7 | 3 | T27 | 1 | T38 | 1 | ||||
others[1] | 528 | 1 | T7 | 8 | T8 | 1 | T30 | 2 | ||||
others[2] | 546 | 1 | T7 | 4 | T8 | 1 | T38 | 1 | ||||
others[3] | 942 | 1 | T7 | 12 | T8 | 1 | T13 | 1 | ||||
false | 10614 | 1 | T1 | 1 | T2 | 2 | T3 | 1 | ||||
true | 2908 | 1 | T2 | 1 | T7 | 1 | T8 | 7 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |