Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

32                      
33         1/1            always_comb reset_or_disable = !rst_slow_ni || disable_sva;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T44,T33

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	17109952	4965	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	17109952	207815	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	17109952	7019359	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	17109952	207800	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	17109952	4965	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	17109952	207815	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	17109952	7019359	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	17109952	207800	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17109952	4965	0	0
T1	1263	1	0	0
T2	1430	0	0	0
T3	5890	0	0	0
T4	7170	0	0	0
T5	2456	0	0	0
T6	2601	0	0	0
T7	3897	0	0	0
T8	6304	0	0	0
T9	12150	9	0	0
T10	1199	0	0	0
T14	0	20	0	0
T33	0	1	0	0
T34	0	1	0	0
T39	0	22	0	0
T40	0	23	0	0
T44	0	3	0	0
T45	0	1	0	0
T86	0	2	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17109952	207815	0	0
T1	1263	13	0	0
T2	1430	0	0	0
T3	5890	0	0	0
T4	7170	0	0	0
T5	2456	0	0	0
T6	2601	0	0	0
T7	3897	0	0	0
T8	6304	0	0	0
T9	12150	336	0	0
T10	1199	0	0	0
T14	0	709	0	0
T33	0	68	0	0
T34	0	10	0	0
T39	0	1228	0	0
T40	0	1317	0	0
T44	0	294	0	0
T45	0	8	0	0
T86	0	22	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17109952	7019359	0	0
T1	1263	967	0	0
T2	1430	0	0	0
T3	5890	3210	0	0
T4	7170	1859	0	0
T5	2456	0	0	0
T6	2601	1069	0	0
T7	3897	0	0	0
T8	6304	0	0	0
T9	12150	5451	0	0
T10	1199	0	0	0
T14	0	15915	0	0
T42	0	2161	0	0
T44	0	249	0	0
T45	0	1237	0	0
T87	0	1362	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17109952	207800	0	0
T1	1263	13	0	0
T2	1430	0	0	0
T3	5890	0	0	0
T4	7170	0	0	0
T5	2456	0	0	0
T6	2601	0	0	0
T7	3897	0	0	0
T8	6304	0	0	0
T9	12150	336	0	0
T10	1199	0	0	0
T14	0	709	0	0
T33	0	68	0	0
T34	0	10	0	0
T39	0	1228	0	0
T40	0	1317	0	0
T44	0	294	0	0
T45	0	8	0	0
T86	0	22	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17109952	4965	0	0
T1	1263	1	0	0
T2	1430	0	0	0
T3	5890	0	0	0
T4	7170	0	0	0
T5	2456	0	0	0
T6	2601	0	0	0
T7	3897	0	0	0
T8	6304	0	0	0
T9	12150	9	0	0
T10	1199	0	0	0
T14	0	20	0	0
T33	0	1	0	0
T34	0	1	0	0
T39	0	22	0	0
T40	0	23	0	0
T44	0	3	0	0
T45	0	1	0	0
T86	0	2	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17109952	207815	0	0
T1	1263	13	0	0
T2	1430	0	0	0
T3	5890	0	0	0
T4	7170	0	0	0
T5	2456	0	0	0
T6	2601	0	0	0
T7	3897	0	0	0
T8	6304	0	0	0
T9	12150	336	0	0
T10	1199	0	0	0
T14	0	709	0	0
T33	0	68	0	0
T34	0	10	0	0
T39	0	1228	0	0
T40	0	1317	0	0
T44	0	294	0	0
T45	0	8	0	0
T86	0	22	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17109952	7019359	0	0
T1	1263	967	0	0
T2	1430	0	0	0
T3	5890	3210	0	0
T4	7170	1859	0	0
T5	2456	0	0	0
T6	2601	1069	0	0
T7	3897	0	0	0
T8	6304	0	0	0
T9	12150	5451	0	0
T10	1199	0	0	0
T14	0	15915	0	0
T42	0	2161	0	0
T44	0	249	0	0
T45	0	1237	0	0
T87	0	1362	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17109952	207800	0	0
T1	1263	13	0	0
T2	1430	0	0	0
T3	5890	0	0	0
T4	7170	0	0	0
T5	2456	0	0	0
T6	2601	0	0	0
T7	3897	0	0	0
T8	6304	0	0	0
T9	12150	336	0	0
T10	1199	0	0	0
T14	0	709	0	0
T33	0	68	0	0
T34	0	10	0	0
T39	0	1228	0	0
T40	0	1317	0	0
T44	0	294	0	0
T45	0	8	0	0
T86	0	22	0	0