Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	17672759	16209	0	0
intr_enable_rd_A	17672759	33403	0	0
reset_en_rd_A	17672759	1672	0	0
reset_en_regwen_rd_A	17672759	1599	0	0
wake_info_capture_dis_rd_A	17672759	1535	0	0
wakeup_en_rd_A	17672759	2087	0	0
wakeup_en_regwen_rd_A	17672759	1556	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17672759	16209	0	0
T23	193090	10	0	0
T24	213135	10	0	0
T25	88735	1	0	0
T56	0	50	0	0
T90	0	28	0	0
T91	0	16	0	0
T92	0	30	0	0
T93	0	13	0	0
T95	2665	0	0	0
T96	7285	0	0	0
T97	30996	0	0	0
T98	506	0	0	0
T99	935	0	0	0
T100	2168	0	0	0
T101	1806	0	0	0
T102	0	61	0	0
T136	0	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17672759	33403	0	0
T7	3897	110	0	0
T8	6304	0	0	0
T9	12150	0	0	0
T10	1199	0	0	0
T11	10737	0	0	0
T13	4628	0	0	0
T14	0	217	0	0
T37	0	16	0	0
T41	763	0	0	0
T42	3847	0	0	0
T44	1391	0	0	0
T45	1687	1	0	0
T49	0	32	0	0
T67	0	37	0	0
T86	0	20	0	0
T89	0	67	0	0
T137	0	180	0	0
T138	0	183	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17672759	1672	0	0
T24	213135	31	0	0
T25	88735	10	0	0
T56	0	33	0	0
T63	0	22	0	0
T76	0	23	0	0
T91	0	4	0	0
T94	0	9	0	0
T98	506	0	0	0
T99	935	0	0	0
T100	2168	0	0	0
T101	1806	0	0	0
T105	55291	0	0	0
T106	3018	0	0	0
T107	5156	0	0	0
T108	4857	0	0	0
T139	0	7	0	0
T140	0	9	0	0
T141	0	10	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17672759	1599	0	0
T24	213135	25	0	0
T25	88735	9	0	0
T56	0	24	0	0
T63	0	17	0	0
T76	0	21	0	0
T91	0	12	0	0
T94	0	5	0	0
T98	506	0	0	0
T99	935	0	0	0
T100	2168	0	0	0
T101	1806	0	0	0
T105	55291	0	0	0
T106	3018	0	0	0
T107	5156	0	0	0
T108	4857	0	0	0
T139	0	9	0	0
T140	0	27	0	0
T141	0	3	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17672759	1535	0	0
T24	213135	20	0	0
T25	88735	8	0	0
T56	0	51	0	0
T63	0	17	0	0
T76	0	19	0	0
T91	0	20	0	0
T94	0	5	0	0
T98	506	0	0	0
T99	935	0	0	0
T100	2168	0	0	0
T101	1806	0	0	0
T105	55291	0	0	0
T106	3018	0	0	0
T107	5156	0	0	0
T108	4857	0	0	0
T140	0	15	0	0
T141	0	7	0	0
T142	0	10	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17672759	2087	0	0
T24	213135	41	0	0
T25	88735	5	0	0
T56	0	29	0	0
T63	0	16	0	0
T76	0	22	0	0
T91	0	25	0	0
T94	0	17	0	0
T98	506	0	0	0
T99	935	0	0	0
T100	2168	0	0	0
T101	1806	0	0	0
T105	55291	0	0	0
T106	3018	0	0	0
T107	5156	0	0	0
T108	4857	0	0	0
T139	0	9	0	0
T140	0	23	0	0
T141	0	16	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17672759	1556	0	0
T24	213135	22	0	0
T25	88735	9	0	0
T56	0	32	0	0
T63	0	14	0	0
T76	0	29	0	0
T91	0	15	0	0
T94	0	21	0	0
T98	506	0	0	0
T99	935	0	0	0
T100	2168	0	0	0
T101	1806	0	0	0
T105	55291	0	0	0
T106	3018	0	0	0
T107	5156	0	0	0
T108	4857	0	0	0
T139	0	13	0	0
T140	0	19	0	0
T141	0	9	0	0