Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	51329856	105973	0	0
StatusRise_A	51329856	119254	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51329856	105973	0	0
T1	3789	6	0	0
T2	4290	6	0	0
T3	17670	55	0	0
T4	21510	54	0	0
T5	7368	3	0	0
T6	7803	33	0	0
T7	11691	3	0	0
T8	18912	69	0	0
T9	36450	90	0	0
T10	3597	0	0	0
T42	0	28	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51329856	119254	0	0
T1	3789	9	0	0
T2	4290	9	0	0
T3	17670	58	0	0
T4	21510	57	0	0
T5	7368	9	0	0
T6	7803	35	0	0
T7	11691	6	0	0
T8	18912	75	0	0
T9	36450	96	0	0
T10	3597	12	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	17109952	39475	0	0
StatusRise_A	17109952	44241	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17109952	39475	0	0
T1	1263	2	0	0
T2	1430	2	0	0
T3	5890	20	0	0
T4	7170	19	0	0
T5	2456	1	0	0
T6	2601	12	0	0
T7	3897	1	0	0
T8	6304	23	0	0
T9	12150	31	0	0
T10	1199	0	0	0
T42	0	11	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17109952	44241	0	0
T1	1263	3	0	0
T2	1430	3	0	0
T3	5890	21	0	0
T4	7170	20	0	0
T5	2456	3	0	0
T6	2601	13	0	0
T7	3897	2	0	0
T8	6304	25	0	0
T9	12150	33	0	0
T10	1199	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	17109952	39476	0	0
StatusRise_A	17109952	44242	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17109952	39476	0	0
T1	1263	2	0	0
T2	1430	2	0	0
T3	5890	20	0	0
T4	7170	19	0	0
T5	2456	1	0	0
T6	2601	12	0	0
T7	3897	1	0	0
T8	6304	23	0	0
T9	12150	31	0	0
T10	1199	0	0	0
T42	0	11	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17109952	44242	0	0
T1	1263	3	0	0
T2	1430	3	0	0
T3	5890	21	0	0
T4	7170	20	0	0
T5	2456	3	0	0
T6	2601	13	0	0
T7	3897	2	0	0
T8	6304	25	0	0
T9	12150	33	0	0
T10	1199	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	17109952	27022	0	0
StatusRise_A	17109952	30771	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17109952	27022	0	0
T1	1263	2	0	0
T2	1430	2	0	0
T3	5890	15	0	0
T4	7170	16	0	0
T5	2456	1	0	0
T6	2601	9	0	0
T7	3897	1	0	0
T8	6304	23	0	0
T9	12150	28	0	0
T10	1199	0	0	0
T42	0	6	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17109952	30771	0	0
T1	1263	3	0	0
T2	1430	3	0	0
T3	5890	16	0	0
T4	7170	17	0	0
T5	2456	3	0	0
T6	2601	9	0	0
T7	3897	2	0	0
T8	6304	25	0	0
T9	12150	30	0	0
T10	1199	4	0	0