Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

41                      
42         1/1            always_comb reset_or_disable = !rst_ni || disable_sva;
           Tests:       T1 T2 T3 
43         1/1            always_comb esc_reset_or_disable = !rst_esc_ni || disable_sva;
           Tests:       T1 T2 T3 
44         1/1            always_comb slow_reset_or_disable = !rst_slow_ni || disable_sva;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	17110503	11336	0	0
EscTimeoutStoppedByClReset_A	17109952	2360859	0	0
EscTimeoutTriggersReset_A	3646093	423	0	0
RomAllowActiveState_A	17109952	43823	0	0
RomAllowCheckGoodState_A	17109952	43872	0	0
RomBlockActiveState_A	17109952	29428	0	0
RomBlockCheckGoodState_A	17109952	363657	0	0
RomIntgChkDisFalse_A	17109952	16567149	0	0
RomIntgChkDisTrue_A	17109952	126266	0	0
RstreqChkEsctimeout_A	17109952	3244	0	0
RstreqChkFsmterm_A	17109952	180	0	0
RstreqChkGlbesc_A	17109952	3244	0	0
RstreqChkMainpd_A	17109952	725371	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17110503	11336	0	0
T11	10737	386	0	0
T14	33385	0	0	0
T15	1985	0	0	0
T27	1741	0	0	0
T31	0	175	0	0
T38	7276	0	0	0
T39	59536	0	0	0
T44	1392	0	0	0
T45	1687	0	0	0
T71	3142	0	0	0
T87	3056	0	0	0
T144	0	10	0	0
T145	0	82	0	0
T146	0	4	0	0
T147	0	66	0	0
T148	0	18	0	0
T149	0	20	0	0
T150	0	500	0	0
T151	0	8	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17109952	2360859	0	0
T1	1263	13	0	0
T2	1430	60	0	0
T3	5890	925	0	0
T4	7170	1950	0	0
T5	2456	39	0	0
T6	2601	38	0	0
T7	3897	27	0	0
T8	6304	827	0	0
T9	12150	2304	0	0
T10	1199	15	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3646093	423	0	0
T5	211	2	0	0
T6	207	0	0	0
T7	1314	0	0	0
T8	492	0	0	0
T9	2555	0	0	0
T10	413	0	0	0
T11	156	5	0	0
T12	0	4	0	0
T13	356	0	0	0
T31	0	5	0	0
T41	270	0	0	0
T42	1720	0	0	0
T144	0	6	0	0
T145	0	5	0	0
T146	0	3	0	0
T147	0	5	0	0
T148	0	6	0	0
T152	0	2	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17109952	43823	0	0
T1	1263	3	0	0
T2	1430	3	0	0
T3	5890	21	0	0
T4	7170	20	0	0
T5	2456	3	0	0
T6	2601	13	0	0
T7	3897	2	0	0
T8	6304	25	0	0
T9	12150	33	0	0
T10	1199	4	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17109952	43872	0	0
T1	1263	3	0	0
T2	1430	3	0	0
T3	5890	21	0	0
T4	7170	20	0	0
T5	2456	3	0	0
T6	2601	13	0	0
T7	3897	2	0	0
T8	6304	25	0	0
T9	12150	33	0	0
T10	1199	4	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17109952	29428	0	0
T11	10737	0	0	0
T13	4628	1079	0	0
T14	33385	0	0	0
T15	1984	0	0	0
T26	0	932	0	0
T27	1741	0	0	0
T38	7275	0	0	0
T44	1391	0	0	0
T45	1687	0	0	0
T52	0	288	0	0
T71	3141	0	0	0
T87	3055	0	0	0
T107	0	804	0	0
T153	0	377	0	0
T154	0	371	0	0
T155	0	15	0	0
T156	0	140	0	0
T157	0	20	0	0
T158	0	576	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17109952	363657	0	0
T9	12150	414	0	0
T10	1199	0	0	0
T11	10737	0	0	0
T13	4628	873	0	0
T14	33385	2191	0	0
T26	0	1048	0	0
T27	1741	0	0	0
T39	0	4130	0	0
T40	0	4143	0	0
T41	763	0	0	0
T42	3847	0	0	0
T44	1391	0	0	0
T45	1687	0	0	0
T72	0	184	0	0
T86	0	115	0	0
T137	0	2258	0	0
T159	0	4033	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17109952	16567149	0	0
T1	1263	1179	0	0
T2	1430	1349	0	0
T3	5890	5826	0	0
T4	7170	7097	0	0
T5	2456	2313	0	0
T6	2601	2548	0	0
T7	3897	3836	0	0
T8	6304	6132	0	0
T9	12150	11992	0	0
T10	1199	876	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17109952	126266	0	0
T11	10737	0	0	0
T13	4628	93	0	0
T14	33385	1764	0	0
T15	1984	0	0	0
T26	0	96	0	0
T27	1741	0	0	0
T38	7275	0	0	0
T44	1391	0	0	0
T45	1687	0	0	0
T52	0	157	0	0
T71	3141	0	0	0
T87	3055	0	0	0
T138	0	805	0	0
T153	0	240	0	0
T154	0	35	0	0
T155	0	951	0	0
T159	0	1380	0	0
T160	0	165	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17109952	3244	0	0
T2	1430	1	0	0
T3	5890	0	0	0
T4	7170	0	0	0
T5	2456	1	0	0
T6	2601	0	0	0
T7	3897	0	0	0
T8	6304	10	0	0
T9	12150	0	0	0
T10	1199	3	0	0
T11	0	2	0	0
T12	0	1	0	0
T13	0	5	0	0
T27	0	3	0	0
T38	0	5	0	0
T41	763	0	0	0
T43	0	5	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17109952	180	0	0
T20	32071	40	0	0
T21	0	40	0	0
T22	0	20	0	0
T26	4724	0	0	0
T28	0	40	0	0
T29	0	40	0	0
T30	6156	0	0	0
T31	9731	0	0	0
T32	14799	0	0	0
T33	1310	0	0	0
T34	1674	0	0	0
T35	6208	0	0	0
T36	3642	0	0	0
T37	2594	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17109952	3244	0	0
T2	1430	1	0	0
T3	5890	0	0	0
T4	7170	0	0	0
T5	2456	1	0	0
T6	2601	0	0	0
T7	3897	0	0	0
T8	6304	10	0	0
T9	12150	0	0	0
T10	1199	3	0	0
T11	0	2	0	0
T12	0	1	0	0
T13	0	5	0	0
T27	0	3	0	0
T38	0	5	0	0
T41	763	0	0	0
T43	0	5	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17109952	725371	0	0
T2	1430	85	0	0
T3	5890	0	0	0
T4	7170	0	0	0
T5	2456	0	0	0
T6	2601	0	0	0
T7	3897	0	0	0
T8	6304	948	0	0
T9	12150	868	0	0
T10	1199	0	0	0
T13	0	946	0	0
T14	0	2783	0	0
T27	0	49	0	0
T38	0	169	0	0
T39	0	4744	0	0
T40	0	5118	0	0
T41	763	6	0	0