Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21696

1

T1

2

T4

4

T5

2

auto[1]

21062

1

T3

4

T4

12

T5

2

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22041

1

T1

2

T3

2

T4

8

auto[1]

20717

1

T3

2

T4

8

T5

2

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20754

1

T3

4

T4

8

T5

2

auto[1]

22004

1

T1

2

T4

8

T5

2

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23900

1

T1

1

T3

2

T4

8

auto[1]

18858

1

T1

1

T3

2

T4

8

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21221

1

T3

4

T4

10

T5

2

auto[1]

21537

1

T1

2

T4

6

T5

2

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21682

1

T1

2

T3

4

T4

4

auto[1]

21076

1

T4

12

T5

3

T7

18

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

719

1

T7

1

T9

1

T34

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

572

1

T7

1

T9

1

T34

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

734

1

T7

1

T9

1

T10

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

576

1

T7

1

T9

1

T17

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

690

1

T7

1

T34

1

T118

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

543

1

T7

1

T34

1

T118

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1198

1

T1

1

T9

1

T34

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1039

1

T1

1

T9

1

T34

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

737

1

T7

2

T28

1

T116

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

589

1

T7

2

T28

1

T116

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

747

1

T9

1

T34

2

T16

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

601

1

T9

1

T34

2

T39

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

717

1

T9

1

T36

1

T99

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

566

1

T9

1

T36

1

T99

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

755

1

T5

1

T7

1

T16

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

597

1

T7

1

T118

1

T39

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

740

1

T7

1

T10

1

T16

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

558

1

T7

1

T10

1

T17

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

747

1

T36

2

T17

3

T28

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

603

1

T36

2

T17

1

T28

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

706

1

T5

1

T33

1

T116

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

551

1

T33

1

T116

1

T117

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

674

1

T7

2

T10

1

T99

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

506

1

T7

2

T10

1

T99

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

694

1

T4

1

T9

2

T39

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

530

1

T4

1

T9

2

T39

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

766

1

T33

1

T34

1

T16

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

610

1

T33

1

T34

1

T28

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

732

1

T7

1

T9

1

T34

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

576

1

T7

1

T9

1

T34

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

743

1

T4

1

T7

1

T16

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

580

1

T4

1

T7

1

T118

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

782

1

T3

1

T4

1

T17

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

633

1

T3

1

T4

1

T17

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

736

1

T9

1

T34

2

T99

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

585

1

T9

1

T34

2

T99

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

715

1

T34

1

T36

1

T99

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

566

1

T34

1

T36

1

T99

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

728

1

T7

1

T36

1

T17

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

581

1

T7

1

T36

1

T17

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

733

1

T4

2

T7

2

T118

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

598

1

T4

2

T7

2

T118

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

750

1

T4

1

T5

1

T99

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

595

1

T4

1

T28

2

T116

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

736

1

T10

1

T99

2

T17

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

583

1

T10

1

T99

1

T17

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

754

1

T7

1

T36

2

T99

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

586

1

T7

1

T36

2

T99

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

744

1

T3

1

T7

1

T16

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

585

1

T3

1

T7

1

T99

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

754

1

T7

2

T9

1

T33

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

594

1

T7

2

T9

1

T17

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

716

1

T7

1

T118

1

T17

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

555

1

T7

1

T118

1

T17

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

718

1

T4

1

T9

1

T34

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

534

1

T4

1

T9

1

T34

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

727

1

T5

1

T34

2

T99

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

563

1

T34

2

T99

1

T28

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

742

1

T7

1

T36

1

T28

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

577

1

T7

1

T36

1

T28

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

737

1

T28

1

T116

3

T26

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

561

1

T28

1

T116

3

T42

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

729

1

T4

1

T34

1

T17

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

565

1

T4

1

T34

1

T17

1