Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.89 98.23 96.58 99.62 96.00 96.37 99.74 98.69


Total tests in report: 1100
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
78.49 78.49 95.66 95.66 84.88 84.88 82.86 82.86 60.00 60.00 92.37 92.37 90.79 90.79 42.88 42.88 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup_reset.2998145796
83.66 5.16 96.31 0.64 85.45 0.57 83.15 0.28 64.00 4.00 92.94 0.57 91.58 0.79 72.18 29.30 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all.2146110427
87.90 4.24 96.71 0.40 85.73 0.29 86.44 3.30 86.00 22.00 93.51 0.57 92.89 1.32 73.98 1.80 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset_invalid.8524589
90.33 2.44 96.95 0.24 87.87 2.14 96.80 10.36 88.00 2.00 94.47 0.95 93.95 1.05 74.30 0.33 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm.1203406746
92.10 1.76 97.11 0.16 90.16 2.28 97.18 0.38 88.00 0.00 94.66 0.19 96.58 2.63 81.01 6.71 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all_with_rand_reset.1588859138
93.50 1.40 97.11 0.00 90.16 0.00 99.06 1.88 88.00 0.00 94.66 0.00 97.11 0.53 88.38 7.36 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2647612517
94.68 1.19 97.11 0.00 90.16 0.00 99.06 0.00 96.00 8.00 94.66 0.00 97.11 0.00 88.71 0.33 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_invalid.552217382
95.51 0.83 97.11 0.00 92.01 1.85 99.06 0.00 96.00 0.00 94.66 0.00 97.11 0.00 92.64 3.93 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.2062359468
96.07 0.56 97.43 0.32 93.58 1.57 99.25 0.19 96.00 0.00 95.42 0.76 98.16 1.05 92.64 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_rw.4150750895
96.39 0.32 97.43 0.00 93.87 0.29 99.25 0.00 96.00 0.00 95.42 0.00 98.16 0.00 94.60 1.96 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.2532589034
96.70 0.31 97.67 0.24 94.01 0.14 99.25 0.00 96.00 0.00 95.42 0.00 98.16 0.00 96.40 1.80 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_intr_test.258153484
96.94 0.24 97.83 0.16 94.44 0.43 99.25 0.00 96.00 0.00 95.99 0.57 98.68 0.53 96.40 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_escalation_timeout.3772840539
97.17 0.23 97.83 0.00 95.86 1.43 99.25 0.00 96.00 0.00 95.99 0.00 98.68 0.00 96.56 0.16 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_errors.2249103949
97.33 0.16 97.83 0.00 95.86 0.00 99.25 0.00 96.00 0.00 96.18 0.19 98.95 0.26 97.22 0.65 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_disable_rom_integrity_check.139102429
97.44 0.11 98.23 0.40 95.86 0.00 99.62 0.38 96.00 0.00 96.18 0.00 98.95 0.00 97.22 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_stress_all_with_rand_reset.650943527
97.53 0.09 98.23 0.00 95.86 0.00 99.62 0.00 96.00 0.00 96.18 0.00 98.95 0.00 97.87 0.65 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2343981153
97.61 0.08 98.23 0.00 95.86 0.00 99.62 0.00 96.00 0.00 96.18 0.00 99.47 0.53 97.87 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.1299426870
97.65 0.05 98.23 0.00 96.01 0.14 99.62 0.00 96.00 0.00 96.37 0.19 99.47 0.00 97.87 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_aborted_low_power.3545350200
97.70 0.05 98.23 0.00 96.01 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.47 0.00 98.20 0.33 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_intr_test.1157256352
97.75 0.04 98.23 0.00 96.15 0.14 99.62 0.00 96.00 0.00 96.37 0.00 99.47 0.00 98.36 0.16 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.1087978888
97.77 0.02 98.23 0.00 96.15 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.47 0.00 98.53 0.16 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_disable_rom_integrity_check.906362293
97.79 0.02 98.23 0.00 96.15 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.47 0.00 98.69 0.16 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_disable_rom_integrity_check.3383988160
97.81 0.02 98.23 0.00 96.29 0.14 99.62 0.00 96.00 0.00 96.37 0.00 99.47 0.00 98.69 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.4171887062
97.83 0.02 98.23 0.00 96.43 0.14 99.62 0.00 96.00 0.00 96.37 0.00 99.47 0.00 98.69 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_glitch.1455695041
97.85 0.02 98.23 0.00 96.58 0.14 99.62 0.00 96.00 0.00 96.37 0.00 99.47 0.00 98.69 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all_with_rand_reset.1263138408

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.865232199
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.1584219701
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.3592883664
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_rw.1153781818
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_intr_test.205095531
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.636904329
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_errors.3128006009
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.3292171646
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.3527548598
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.3087027792
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.768349757
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.2675884893
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_rw.1745652775
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_intr_test.458909405
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.908194043
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_errors.2937662168
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.742327862
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.4026569937
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_rw.3799388601
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.3661271410
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_errors.3808603990
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.757253205
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.333595299
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_rw.852298964
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_intr_test.2206444472
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.191271644
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_errors.1330228235
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.3651918592
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.2373026713
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_rw.3023013465
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_intr_test.869006686
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.3384144799
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_errors.2825227619
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.1686550248
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_rw.243442227
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_intr_test.384851670
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.3707022069
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_errors.1281267652
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.72684752
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.1067447404
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_rw.2569901981
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.2415416512
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_errors.1216632128
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.2648039468
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.2675881322
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_rw.1760617517
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_intr_test.1426225627
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.707768383
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_errors.1218439249
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.566360644
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.2909100896
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_rw.4181466818
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_intr_test.657862869
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.756826768
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_errors.2230090216
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.3649776861
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.3198265639
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_rw.2203040294
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_intr_test.550277016
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.702141589
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_errors.4171194088
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.1650338557
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.3540944943
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_rw.4039161097
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_intr_test.3474550962
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.753016459
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_errors.1095799769
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.3787621013
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.2029871058
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_rw.3790417759
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_intr_test.936767314
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.2734292343
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_errors.3284709783
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.422204863
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.1558403155
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.1641936510
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.1294783779
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.1229873837
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_rw.1526066940
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_intr_test.1398136221
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.2555390721
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.2210977063
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/20.pwrmgr_intr_test.2337946755
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/21.pwrmgr_intr_test.1774966743
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/22.pwrmgr_intr_test.3028808698
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/23.pwrmgr_intr_test.2598058255
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/24.pwrmgr_intr_test.2452606008
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/25.pwrmgr_intr_test.1655176786
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/26.pwrmgr_intr_test.1314897401
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/27.pwrmgr_intr_test.3916794976
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/28.pwrmgr_intr_test.3516270024
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/cover_reg_top/29.pwrmgr_intr_test.2596227634
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/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup.800568990
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup_reset.2331436120
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_aborted_low_power.409995859
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_disable_rom_integrity_check.4009259716
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.1386652037
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/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_global_esc.3083202640
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_invalid.1812365062
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_wakeup_race.2449284859
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset.3493120033
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset_invalid.3236708263
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.3770392714
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.978510963
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3374783274
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.3524425782
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_smoke.1553272317
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all.3094088104
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all_with_rand_reset.3313162787
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup.175005400
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup_reset.3456375566
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_aborted_low_power.3201560555
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_disable_rom_integrity_check.3405022171
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.2546901639
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_escalation_timeout.1987768574
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_glitch.3590718176
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_global_esc.3950154426
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_invalid.2979626653
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_wakeup_race.13456061
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset.2816290641
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset_invalid.1671224629
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.1447508036
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4251059593
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1800441668
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.4187961517
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_smoke.3319604151
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all.920409399
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all_with_rand_reset.1965075985
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup.55026296
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup_reset.380291780
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_aborted_low_power.1297671988
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_disable_rom_integrity_check.3416818010
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.140539878
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_escalation_timeout.2580251663
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_glitch.4054479321
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_global_esc.2011724655
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_invalid.3175655706
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_wakeup_race.1635066535
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset.166833627
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset_invalid.3928237151
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.2949417851
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2924150670
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3590920503
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.3497899593
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_smoke.888580291
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all.3925899678
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all_with_rand_reset.3160439975
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup.4199717987
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup_reset.3407636608
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_aborted_low_power.697546867
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_disable_rom_integrity_check.1436421448
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.188726799
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_escalation_timeout.2499732118
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_glitch.419378123
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_global_esc.1921885280
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_invalid.3225438646
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_wakeup_race.604321127
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset.429097303
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset_invalid.3463316385
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.3928029457
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3938852364
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1738459650
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.4174196275
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_smoke.3641481434
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all.3809913370
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup.3724489155
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup_reset.3274334804
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_aborted_low_power.2263885173
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_disable_rom_integrity_check.3456462969
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.711841727
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_escalation_timeout.791942158
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_glitch.731223990
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_global_esc.965480587
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_invalid.3439426178
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_wakeup_race.1690987889
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset.3255298316
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset_invalid.220431121
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.3647774825
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.59688432
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4193073475
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.3427286621
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_smoke.1768457243
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all.1998020062
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all_with_rand_reset.3103692958
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup.1395506486
/workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup_reset.1157883864



Total test records in report: 1100
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_smoke.1021527971 Aug 27 05:15:35 AM UTC 24 Aug 27 05:15:37 AM UTC 24 28987164 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset.1606507605 Aug 27 05:15:48 AM UTC 24 Aug 27 05:15:50 AM UTC 24 61117248 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_wakeup_race.3921669793 Aug 27 05:15:48 AM UTC 24 Aug 27 05:15:50 AM UTC 24 105889743 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup_reset.3669103597 Aug 27 05:15:53 AM UTC 24 Aug 27 05:15:55 AM UTC 24 117986792 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_aborted_low_power.3545350200 Aug 27 05:15:48 AM UTC 24 Aug 27 05:15:50 AM UTC 24 22909150 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.1532742192 Aug 27 05:15:48 AM UTC 24 Aug 27 05:15:50 AM UTC 24 38337957 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_wakeup_race.1212067254 Aug 27 05:15:53 AM UTC 24 Aug 27 05:15:55 AM UTC 24 308334685 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_global_esc.3797120728 Aug 27 05:15:48 AM UTC 24 Aug 27 05:15:50 AM UTC 24 32068692 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup_reset.2998145796 Aug 27 05:15:48 AM UTC 24 Aug 27 05:15:50 AM UTC 24 383616499 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.753171214 Aug 27 05:15:48 AM UTC 24 Aug 27 05:15:50 AM UTC 24 79030987 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm.1203406746 Aug 27 05:15:53 AM UTC 24 Aug 27 05:15:55 AM UTC 24 728761739 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_glitch.714171537 Aug 27 05:15:48 AM UTC 24 Aug 27 05:15:50 AM UTC 24 49573586 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.1021540809 Aug 27 05:15:48 AM UTC 24 Aug 27 05:15:50 AM UTC 24 70001170 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_invalid.552217382 Aug 27 05:15:48 AM UTC 24 Aug 27 05:15:50 AM UTC 24 58941958 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup.742344102 Aug 27 05:15:48 AM UTC 24 Aug 27 05:15:50 AM UTC 24 224392191 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_escalation_timeout.3772840539 Aug 27 05:15:48 AM UTC 24 Aug 27 05:15:50 AM UTC 24 208556006 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_smoke.1085156807 Aug 27 05:15:49 AM UTC 24 Aug 27 05:15:50 AM UTC 24 36240416 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup.422546060 Aug 27 05:15:49 AM UTC 24 Aug 27 05:15:50 AM UTC 24 178539163 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_disable_rom_integrity_check.1093329101 Aug 27 05:15:48 AM UTC 24 Aug 27 05:15:50 AM UTC 24 73405360 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset_invalid.8524589 Aug 27 05:15:48 AM UTC 24 Aug 27 05:15:51 AM UTC 24 90448541 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.4168703813 Aug 27 05:15:49 AM UTC 24 Aug 27 05:15:51 AM UTC 24 60229225 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_global_esc.1251424930 Aug 27 05:15:49 AM UTC 24 Aug 27 05:15:51 AM UTC 24 96926638 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset.550074728 Aug 27 05:15:49 AM UTC 24 Aug 27 05:15:51 AM UTC 24 80152983 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_escalation_timeout.3366342504 Aug 27 05:15:49 AM UTC 24 Aug 27 05:15:51 AM UTC 24 594363245 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_aborted_low_power.4140351115 Aug 27 05:15:49 AM UTC 24 Aug 27 05:15:51 AM UTC 24 34692999 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_glitch.1455695041 Aug 27 05:15:49 AM UTC 24 Aug 27 05:15:51 AM UTC 24 55823013 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.2532589034 Aug 27 05:15:49 AM UTC 24 Aug 27 05:15:51 AM UTC 24 190995459 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_disable_rom_integrity_check.109713841 Aug 27 05:15:49 AM UTC 24 Aug 27 05:15:51 AM UTC 24 67309456 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_wakeup_race.3402747113 Aug 27 05:15:49 AM UTC 24 Aug 27 05:15:51 AM UTC 24 215283728 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.2671155559 Aug 27 05:15:49 AM UTC 24 Aug 27 05:15:51 AM UTC 24 64749659 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset_invalid.2111909170 Aug 27 05:15:49 AM UTC 24 Aug 27 05:15:51 AM UTC 24 166796727 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup_reset.3845418163 Aug 27 05:15:49 AM UTC 24 Aug 27 05:15:51 AM UTC 24 198622117 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all.2146110427 Aug 27 05:15:48 AM UTC 24 Aug 27 05:15:51 AM UTC 24 475230483 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2647612517 Aug 27 05:15:48 AM UTC 24 Aug 27 05:15:51 AM UTC 24 1606773651 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm.533435123 Aug 27 05:15:48 AM UTC 24 Aug 27 05:15:52 AM UTC 24 636147298 ps
T116 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.671721596 Aug 27 05:15:49 AM UTC 24 Aug 27 05:15:52 AM UTC 24 950331463 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2343981153 Aug 27 05:15:48 AM UTC 24 Aug 27 05:15:52 AM UTC 24 885946536 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_smoke.1952748148 Aug 27 05:15:51 AM UTC 24 Aug 27 05:15:53 AM UTC 24 42675480 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_invalid.3324440728 Aug 27 05:15:51 AM UTC 24 Aug 27 05:15:53 AM UTC 24 104897347 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_wakeup_race.1702795505 Aug 27 05:15:51 AM UTC 24 Aug 27 05:15:53 AM UTC 24 270524348 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.3967917633 Aug 27 05:15:51 AM UTC 24 Aug 27 05:15:53 AM UTC 24 81559433 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_aborted_low_power.1139986272 Aug 27 05:15:53 AM UTC 24 Aug 27 05:15:55 AM UTC 24 43580946 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all.726444393 Aug 27 05:15:51 AM UTC 24 Aug 27 05:15:56 AM UTC 24 6612839741 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2052267230 Aug 27 05:15:49 AM UTC 24 Aug 27 05:15:53 AM UTC 24 829585579 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_global_esc.2305248902 Aug 27 05:15:51 AM UTC 24 Aug 27 05:15:53 AM UTC 24 37662404 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset.3894977653 Aug 27 05:15:51 AM UTC 24 Aug 27 05:15:53 AM UTC 24 98602923 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_aborted_low_power.4162224656 Aug 27 05:15:51 AM UTC 24 Aug 27 05:15:53 AM UTC 24 26459998 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_glitch.750053725 Aug 27 05:15:51 AM UTC 24 Aug 27 05:15:53 AM UTC 24 67308042 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.1387906928 Aug 27 05:15:51 AM UTC 24 Aug 27 05:15:53 AM UTC 24 231142648 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup_reset.46109846 Aug 27 05:15:51 AM UTC 24 Aug 27 05:15:53 AM UTC 24 340917595 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup.1319683830 Aug 27 05:15:51 AM UTC 24 Aug 27 05:15:53 AM UTC 24 219876359 ps
T126 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_escalation_timeout.4047381092 Aug 27 05:15:51 AM UTC 24 Aug 27 05:15:53 AM UTC 24 115179613 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm.4252265997 Aug 27 05:15:51 AM UTC 24 Aug 27 05:15:53 AM UTC 24 307391151 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.2538354311 Aug 27 05:15:51 AM UTC 24 Aug 27 05:15:53 AM UTC 24 230455156 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all_with_rand_reset.1588859138 Aug 27 05:15:51 AM UTC 24 Aug 27 05:15:54 AM UTC 24 371218395 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1702728739 Aug 27 05:15:51 AM UTC 24 Aug 27 05:15:54 AM UTC 24 1193106954 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1039470752 Aug 27 05:15:51 AM UTC 24 Aug 27 05:15:54 AM UTC 24 1348973929 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset_invalid.2847077922 Aug 27 05:15:56 AM UTC 24 Aug 27 05:15:57 AM UTC 24 117029486 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all_with_rand_reset.3407349915 Aug 27 05:15:48 AM UTC 24 Aug 27 05:15:54 AM UTC 24 1169430239 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_smoke.1492619225 Aug 27 05:15:53 AM UTC 24 Aug 27 05:15:54 AM UTC 24 48766188 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_disable_rom_integrity_check.139102429 Aug 27 05:15:53 AM UTC 24 Aug 27 05:15:54 AM UTC 24 90940380 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_invalid.2437543208 Aug 27 05:15:53 AM UTC 24 Aug 27 05:15:55 AM UTC 24 100054110 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset.3049276035 Aug 27 05:15:53 AM UTC 24 Aug 27 05:15:55 AM UTC 24 99431696 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup.3248485309 Aug 27 05:15:53 AM UTC 24 Aug 27 05:15:55 AM UTC 24 211915493 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset_invalid.1778494024 Aug 27 05:15:53 AM UTC 24 Aug 27 05:15:55 AM UTC 24 106313556 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.1604565765 Aug 27 05:15:53 AM UTC 24 Aug 27 05:15:55 AM UTC 24 68921085 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1372712085 Aug 27 05:15:53 AM UTC 24 Aug 27 05:15:56 AM UTC 24 1018379145 ps
T142 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3594698720 Aug 27 05:15:53 AM UTC 24 Aug 27 05:15:56 AM UTC 24 868261684 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all.4286296788 Aug 27 05:15:53 AM UTC 24 Aug 27 05:15:57 AM UTC 24 826165399 ps
T173 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_global_esc.2616386076 Aug 27 05:15:55 AM UTC 24 Aug 27 05:15:57 AM UTC 24 80097456 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.4261793324 Aug 27 05:15:55 AM UTC 24 Aug 27 05:15:57 AM UTC 24 46059147 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_escalation_timeout.872972414 Aug 27 05:15:56 AM UTC 24 Aug 27 05:15:57 AM UTC 24 386314355 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_glitch.1833249706 Aug 27 05:15:56 AM UTC 24 Aug 27 05:15:57 AM UTC 24 60837335 ps
T174 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_invalid.4035365288 Aug 27 05:15:56 AM UTC 24 Aug 27 05:15:57 AM UTC 24 77166814 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_disable_rom_integrity_check.2824748175 Aug 27 05:15:56 AM UTC 24 Aug 27 05:15:57 AM UTC 24 62474049 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup.1055619855 Aug 27 05:15:56 AM UTC 24 Aug 27 05:15:57 AM UTC 24 197421986 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_smoke.2126509674 Aug 27 05:15:56 AM UTC 24 Aug 27 05:15:58 AM UTC 24 60277344 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.2028359851 Aug 27 05:15:55 AM UTC 24 Aug 27 05:15:58 AM UTC 24 169424224 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset.3645273879 Aug 27 05:15:56 AM UTC 24 Aug 27 05:15:58 AM UTC 24 103942762 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset.429097303 Aug 27 05:16:04 AM UTC 24 Aug 27 05:16:06 AM UTC 24 26604974 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_smoke.3641481434 Aug 27 05:16:04 AM UTC 24 Aug 27 05:16:06 AM UTC 24 42934256 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_aborted_low_power.697546867 Aug 27 05:16:04 AM UTC 24 Aug 27 05:16:06 AM UTC 24 17368442 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_glitch.419378123 Aug 27 05:16:06 AM UTC 24 Aug 27 05:16:08 AM UTC 24 38726508 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_aborted_low_power.771616212 Aug 27 05:15:56 AM UTC 24 Aug 27 05:15:58 AM UTC 24 24034608 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_wakeup_race.1271960228 Aug 27 05:15:56 AM UTC 24 Aug 27 05:15:58 AM UTC 24 162768761 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.606114249 Aug 27 05:15:56 AM UTC 24 Aug 27 05:15:58 AM UTC 24 30389932 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_global_esc.161468730 Aug 27 05:15:56 AM UTC 24 Aug 27 05:15:58 AM UTC 24 35798647 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.1994441709 Aug 27 05:15:56 AM UTC 24 Aug 27 05:15:58 AM UTC 24 75152313 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_ctrl_config_regwen.4093259713 Aug 27 05:15:56 AM UTC 24 Aug 27 05:15:58 AM UTC 24 56403065 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_glitch.848969343 Aug 27 05:15:56 AM UTC 24 Aug 27 05:15:58 AM UTC 24 47110308 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_invalid.3683356736 Aug 27 05:15:56 AM UTC 24 Aug 27 05:15:58 AM UTC 24 144301715 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_disable_rom_integrity_check.1428302051 Aug 27 05:15:56 AM UTC 24 Aug 27 05:15:58 AM UTC 24 70876361 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm.1885797980 Aug 27 05:15:56 AM UTC 24 Aug 27 05:15:58 AM UTC 24 370952081 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup_reset.224647496 Aug 27 05:15:56 AM UTC 24 Aug 27 05:15:58 AM UTC 24 482815497 ps
T128 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_escalation_timeout.1061252430 Aug 27 05:15:56 AM UTC 24 Aug 27 05:15:58 AM UTC 24 1889959835 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset_invalid.1570379561 Aug 27 05:15:56 AM UTC 24 Aug 27 05:15:58 AM UTC 24 119419224 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all.305155745 Aug 27 05:15:56 AM UTC 24 Aug 27 05:15:58 AM UTC 24 1026839907 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm.2207886547 Aug 27 05:15:56 AM UTC 24 Aug 27 05:15:59 AM UTC 24 924668166 ps
T143 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3753872326 Aug 27 05:15:56 AM UTC 24 Aug 27 05:15:59 AM UTC 24 847824258 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4111222505 Aug 27 05:15:56 AM UTC 24 Aug 27 05:16:00 AM UTC 24 906138565 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_smoke.1553272317 Aug 27 05:15:59 AM UTC 24 Aug 27 05:16:00 AM UTC 24 59716227 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_global_esc.3083202640 Aug 27 05:15:59 AM UTC 24 Aug 27 05:16:01 AM UTC 24 51496887 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup.175005400 Aug 27 05:15:59 AM UTC 24 Aug 27 05:16:01 AM UTC 24 107491329 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_wakeup_race.2449284859 Aug 27 05:15:59 AM UTC 24 Aug 27 05:16:01 AM UTC 24 286165547 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.1386652037 Aug 27 05:15:59 AM UTC 24 Aug 27 05:16:01 AM UTC 24 57337056 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_aborted_low_power.409995859 Aug 27 05:15:59 AM UTC 24 Aug 27 05:16:01 AM UTC 24 71208863 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset.3493120033 Aug 27 05:15:59 AM UTC 24 Aug 27 05:16:01 AM UTC 24 68687520 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_glitch.2809589776 Aug 27 05:15:59 AM UTC 24 Aug 27 05:16:01 AM UTC 24 57000890 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.3524425782 Aug 27 05:15:59 AM UTC 24 Aug 27 05:16:01 AM UTC 24 52731763 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_global_esc.1921885280 Aug 27 05:16:04 AM UTC 24 Aug 27 05:16:06 AM UTC 24 68315661 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_invalid.1812365062 Aug 27 05:15:59 AM UTC 24 Aug 27 05:16:01 AM UTC 24 46129159 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.3770392714 Aug 27 05:15:59 AM UTC 24 Aug 27 05:16:01 AM UTC 24 163558779 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_wakeup_race.13456061 Aug 27 05:15:59 AM UTC 24 Aug 27 05:16:01 AM UTC 24 206999586 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset_invalid.3236708263 Aug 27 05:15:59 AM UTC 24 Aug 27 05:16:01 AM UTC 24 182867881 ps
T129 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_escalation_timeout.564440883 Aug 27 05:15:59 AM UTC 24 Aug 27 05:16:01 AM UTC 24 116455427 ps
T130 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.2546901639 Aug 27 05:15:59 AM UTC 24 Aug 27 05:16:01 AM UTC 24 76348194 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_smoke.3319604151 Aug 27 05:15:59 AM UTC 24 Aug 27 05:16:01 AM UTC 24 32978293 ps
T139 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_disable_rom_integrity_check.4009259716 Aug 27 05:15:59 AM UTC 24 Aug 27 05:16:01 AM UTC 24 49558431 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup.55026296 Aug 27 05:15:59 AM UTC 24 Aug 27 05:16:01 AM UTC 24 197960759 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset.2816290641 Aug 27 05:15:59 AM UTC 24 Aug 27 05:16:01 AM UTC 24 151550889 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup_reset.3456375566 Aug 27 05:15:59 AM UTC 24 Aug 27 05:16:01 AM UTC 24 303429313 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_aborted_low_power.3201560555 Aug 27 05:15:59 AM UTC 24 Aug 27 05:16:01 AM UTC 24 31732011 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup_reset.380291780 Aug 27 05:15:59 AM UTC 24 Aug 27 05:16:01 AM UTC 24 327943970 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.4187961517 Aug 27 05:15:59 AM UTC 24 Aug 27 05:16:01 AM UTC 24 83638579 ps
T140 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.978510963 Aug 27 05:15:59 AM UTC 24 Aug 27 05:16:02 AM UTC 24 971263959 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3374783274 Aug 27 05:15:59 AM UTC 24 Aug 27 05:16:02 AM UTC 24 1236956898 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.1447508036 Aug 27 05:16:01 AM UTC 24 Aug 27 05:16:02 AM UTC 24 182837928 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_global_esc.3950154426 Aug 27 05:16:01 AM UTC 24 Aug 27 05:16:03 AM UTC 24 59063636 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_glitch.3590718176 Aug 27 05:16:01 AM UTC 24 Aug 27 05:16:03 AM UTC 24 52015405 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all.124165610 Aug 27 05:15:56 AM UTC 24 Aug 27 05:16:03 AM UTC 24 1318961650 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_invalid.2979626653 Aug 27 05:16:01 AM UTC 24 Aug 27 05:16:03 AM UTC 24 75615647 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_disable_rom_integrity_check.3405022171 Aug 27 05:16:01 AM UTC 24 Aug 27 05:16:03 AM UTC 24 58211663 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1800441668 Aug 27 05:15:59 AM UTC 24 Aug 27 05:16:03 AM UTC 24 1312772253 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all.3094088104 Aug 27 05:15:59 AM UTC 24 Aug 27 05:16:03 AM UTC 24 667162888 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset_invalid.1671224629 Aug 27 05:16:01 AM UTC 24 Aug 27 05:16:03 AM UTC 24 167296971 ps
T131 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_escalation_timeout.1987768574 Aug 27 05:16:01 AM UTC 24 Aug 27 05:16:03 AM UTC 24 388750698 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4251059593 Aug 27 05:15:59 AM UTC 24 Aug 27 05:16:03 AM UTC 24 883460705 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup.3724489155 Aug 27 05:16:04 AM UTC 24 Aug 27 05:16:06 AM UTC 24 186522686 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_smoke.888580291 Aug 27 05:16:03 AM UTC 24 Aug 27 05:16:05 AM UTC 24 78742053 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_wakeup_race.1635066535 Aug 27 05:16:03 AM UTC 24 Aug 27 05:16:05 AM UTC 24 139759068 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset.166833627 Aug 27 05:16:03 AM UTC 24 Aug 27 05:16:05 AM UTC 24 131828973 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_global_esc.2011724655 Aug 27 05:16:04 AM UTC 24 Aug 27 05:16:05 AM UTC 24 60490789 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.140539878 Aug 27 05:16:04 AM UTC 24 Aug 27 05:16:05 AM UTC 24 39598318 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.3497899593 Aug 27 05:16:04 AM UTC 24 Aug 27 05:16:05 AM UTC 24 69420696 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all.3925899678 Aug 27 05:16:04 AM UTC 24 Aug 27 05:16:07 AM UTC 24 1561300608 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup.4199717987 Aug 27 05:16:03 AM UTC 24 Aug 27 05:16:05 AM UTC 24 464414714 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.2949417851 Aug 27 05:16:04 AM UTC 24 Aug 27 05:16:05 AM UTC 24 114038397 ps
T227 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_glitch.4054479321 Aug 27 05:16:04 AM UTC 24 Aug 27 05:16:05 AM UTC 24 51124868 ps
T228 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset_invalid.3928237151 Aug 27 05:16:04 AM UTC 24 Aug 27 05:16:06 AM UTC 24 105789737 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup_reset.3407636608 Aug 27 05:16:03 AM UTC 24 Aug 27 05:16:05 AM UTC 24 130054890 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_aborted_low_power.1297671988 Aug 27 05:16:03 AM UTC 24 Aug 27 05:16:05 AM UTC 24 30016027 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_invalid.3175655706 Aug 27 05:16:04 AM UTC 24 Aug 27 05:16:06 AM UTC 24 99633732 ps
T132 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_escalation_timeout.2580251663 Aug 27 05:16:04 AM UTC 24 Aug 27 05:16:06 AM UTC 24 214489242 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_disable_rom_integrity_check.3416818010 Aug 27 05:16:04 AM UTC 24 Aug 27 05:16:06 AM UTC 24 59498813 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup_reset.3274334804 Aug 27 05:16:04 AM UTC 24 Aug 27 05:16:06 AM UTC 24 193382838 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.188726799 Aug 27 05:16:04 AM UTC 24 Aug 27 05:16:06 AM UTC 24 32745302 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.4174196275 Aug 27 05:16:04 AM UTC 24 Aug 27 05:16:06 AM UTC 24 147723819 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.3928029457 Aug 27 05:16:04 AM UTC 24 Aug 27 05:16:06 AM UTC 24 216870728 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_wakeup_race.604321127 Aug 27 05:16:04 AM UTC 24 Aug 27 05:16:06 AM UTC 24 174346405 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all_with_rand_reset.2806770847 Aug 27 05:15:56 AM UTC 24 Aug 27 05:16:06 AM UTC 24 7283144313 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all_with_rand_reset.3313162787 Aug 27 05:15:59 AM UTC 24 Aug 27 05:16:07 AM UTC 24 1722265871 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2924150670 Aug 27 05:16:04 AM UTC 24 Aug 27 05:16:07 AM UTC 24 1203829916 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3938852364 Aug 27 05:16:04 AM UTC 24 Aug 27 05:16:07 AM UTC 24 954109630 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1738459650 Aug 27 05:16:04 AM UTC 24 Aug 27 05:16:07 AM UTC 24 904503182 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3590920503 Aug 27 05:16:04 AM UTC 24 Aug 27 05:16:07 AM UTC 24 731207209 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_disable_rom_integrity_check.1436421448 Aug 27 05:16:06 AM UTC 24 Aug 27 05:16:08 AM UTC 24 67729903 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_disable_rom_integrity_check.906362293 Aug 27 05:16:12 AM UTC 24 Aug 27 05:16:14 AM UTC 24 68238528 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all_with_rand_reset.3160439975 Aug 27 05:16:04 AM UTC 24 Aug 27 05:16:08 AM UTC 24 1831549833 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_invalid.3225438646 Aug 27 05:16:06 AM UTC 24 Aug 27 05:16:08 AM UTC 24 81867451 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset_invalid.3463316385 Aug 27 05:16:06 AM UTC 24 Aug 27 05:16:08 AM UTC 24 125988637 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_stress_all.1930537900 Aug 27 05:16:12 AM UTC 24 Aug 27 05:16:16 AM UTC 24 985935415 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_escalation_timeout.2499732118 Aug 27 05:16:06 AM UTC 24 Aug 27 05:16:08 AM UTC 24 111137935 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_smoke.1768457243 Aug 27 05:16:07 AM UTC 24 Aug 27 05:16:08 AM UTC 24 28909004 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.711841727 Aug 27 05:16:07 AM UTC 24 Aug 27 05:16:08 AM UTC 24 29366746 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_aborted_low_power.2263885173 Aug 27 05:16:07 AM UTC 24 Aug 27 05:16:09 AM UTC 24 68845996 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset.3255298316 Aug 27 05:16:07 AM UTC 24 Aug 27 05:16:09 AM UTC 24 73889127 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_global_esc.965480587 Aug 27 05:16:07 AM UTC 24 Aug 27 05:16:09 AM UTC 24 84666491 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup.1395506486 Aug 27 05:16:07 AM UTC 24 Aug 27 05:16:09 AM UTC 24 229609858 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_wakeup_race.1690987889 Aug 27 05:16:07 AM UTC 24 Aug 27 05:16:09 AM UTC 24 188963976 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_glitch.731223990 Aug 27 05:16:07 AM UTC 24 Aug 27 05:16:09 AM UTC 24 63022188 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup_reset.1157883864 Aug 27 05:16:07 AM UTC 24 Aug 27 05:16:09 AM UTC 24 373432687 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_invalid.3439426178 Aug 27 05:16:07 AM UTC 24 Aug 27 05:16:09 AM UTC 24 65723216 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.3427286621 Aug 27 05:16:07 AM UTC 24 Aug 27 05:16:09 AM UTC 24 53449119 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_escalation_timeout.791942158 Aug 27 05:16:07 AM UTC 24 Aug 27 05:16:09 AM UTC 24 207945008 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_disable_rom_integrity_check.3456462969 Aug 27 05:16:07 AM UTC 24 Aug 27 05:16:09 AM UTC 24 59289383 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.3647774825 Aug 27 05:16:07 AM UTC 24 Aug 27 05:16:09 AM UTC 24 390910054 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset_invalid.220431121 Aug 27 05:16:07 AM UTC 24 Aug 27 05:16:09 AM UTC 24 93722419 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.59688432 Aug 27 05:16:07 AM UTC 24 Aug 27 05:16:10 AM UTC 24 1602976667 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all.920409399 Aug 27 05:16:03 AM UTC 24 Aug 27 05:16:10 AM UTC 24 1703971465 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4193073475 Aug 27 05:16:07 AM UTC 24 Aug 27 05:16:11 AM UTC 24 868682702 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all_with_rand_reset.2714326916 Aug 27 05:15:56 AM UTC 24 Aug 27 05:16:11 AM UTC 24 12577713277 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_smoke.804505000 Aug 27 05:16:10 AM UTC 24 Aug 27 05:16:12 AM UTC 24 29583763 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset.1543370533 Aug 27 05:16:10 AM UTC 24 Aug 27 05:16:12 AM UTC 24 25776542 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.883649826 Aug 27 05:16:10 AM UTC 24 Aug 27 05:16:12 AM UTC 24 28227206 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_glitch.3655703371 Aug 27 05:16:10 AM UTC 24 Aug 27 05:16:12 AM UTC 24 62235325 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup_reset.3529023505 Aug 27 05:16:10 AM UTC 24 Aug 27 05:16:12 AM UTC 24 600375904 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_invalid.3278052686 Aug 27 05:16:12 AM UTC 24 Aug 27 05:16:14 AM UTC 24 53487664 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_smoke.343282830 Aug 27 05:16:16 AM UTC 24 Aug 27 05:16:18 AM UTC 24 52691559 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_wakeup_race.935843822 Aug 27 05:16:10 AM UTC 24 Aug 27 05:16:12 AM UTC 24 73391322 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_global_esc.394706738 Aug 27 05:16:10 AM UTC 24 Aug 27 05:16:12 AM UTC 24 43872973 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset.1517301288 Aug 27 05:16:16 AM UTC 24 Aug 27 05:16:18 AM UTC 24 482854914 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_disable_rom_integrity_check.2702734908 Aug 27 05:16:10 AM UTC 24 Aug 27 05:16:12 AM UTC 24 55010824 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.1254078121 Aug 27 05:16:10 AM UTC 24 Aug 27 05:16:12 AM UTC 24 70304456 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_ctrl_config_regwen.2784613209 Aug 27 05:16:10 AM UTC 24 Aug 27 05:16:12 AM UTC 24 287811769 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup.2785323809 Aug 27 05:16:10 AM UTC 24 Aug 27 05:16:12 AM UTC 24 197388665 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset_invalid.3506988054 Aug 27 05:16:10 AM UTC 24 Aug 27 05:16:12 AM UTC 24 156442622 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_aborted_low_power.4248814543 Aug 27 05:16:10 AM UTC 24 Aug 27 05:16:12 AM UTC 24 112712838 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_smoke.2210288308 Aug 27 05:16:10 AM UTC 24 Aug 27 05:16:12 AM UTC 24 35514892 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup_reset.477159237 Aug 27 05:16:10 AM UTC 24 Aug 27 05:16:12 AM UTC 24 126287187 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_invalid.1176957481 Aug 27 05:16:10 AM UTC 24 Aug 27 05:16:13 AM UTC 24 43518310 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all_with_rand_reset.187120359 Aug 27 05:15:53 AM UTC 24 Aug 27 05:16:14 AM UTC 24 4755845142 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.59906524 Aug 27 05:16:11 AM UTC 24 Aug 27 05:16:13 AM UTC 24 28060494 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_escalation_timeout.3230438147 Aug 27 05:16:10 AM UTC 24 Aug 27 05:16:13 AM UTC 24 115858020 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_glitch.3824684313 Aug 27 05:16:11 AM UTC 24 Aug 27 05:16:13 AM UTC 24 58305009 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup.560627269 Aug 27 05:16:10 AM UTC 24 Aug 27 05:16:13 AM UTC 24 338625968 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all.3809913370 Aug 27 05:16:06 AM UTC 24 Aug 27 05:16:13 AM UTC 24 1483860112 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_global_esc.3126633665 Aug 27 05:16:11 AM UTC 24 Aug 27 05:16:13 AM UTC 24 33814670 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_wakeup_race.3620970020 Aug 27 05:16:10 AM UTC 24 Aug 27 05:16:13 AM UTC 24 565586559 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_escalation_timeout.1604559034 Aug 27 05:16:11 AM UTC 24 Aug 27 05:16:13 AM UTC 24 395510356 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_aborted_low_power.1369608491 Aug 27 05:16:11 AM UTC 24 Aug 27 05:16:13 AM UTC 24 30009728 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset.1555399779 Aug 27 05:16:10 AM UTC 24 Aug 27 05:16:13 AM UTC 24 76374893 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.368393190 Aug 27 05:16:11 AM UTC 24 Aug 27 05:16:13 AM UTC 24 109755737 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all_with_rand_reset.1965075985 Aug 27 05:16:03 AM UTC 24 Aug 27 05:16:13 AM UTC 24 6309849464 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.1306440426 Aug 27 05:16:11 AM UTC 24 Aug 27 05:16:13 AM UTC 24 110665799 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all.1088589354 Aug 27 05:16:10 AM UTC 24 Aug 27 05:16:13 AM UTC 24 641650467 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all.1998020062 Aug 27 05:16:10 AM UTC 24 Aug 27 05:16:13 AM UTC 24 460191430 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1230827958 Aug 27 05:16:10 AM UTC 24 Aug 27 05:16:13 AM UTC 24 908516433 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset_invalid.1089230829 Aug 27 05:16:12 AM UTC 24 Aug 27 05:16:14 AM UTC 24 290861778 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3544000480 Aug 27 05:16:10 AM UTC 24 Aug 27 05:16:14 AM UTC 24 922374781 ps
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T304 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_lowpower_invalid.2782786007 Aug 27 05:16:21 AM UTC 24 Aug 27 05:16:23 AM UTC 24 37463170 ps
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T306 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_glitch.2598975426 Aug 27 05:16:16 AM UTC 24 Aug 27 05:16:18 AM UTC 24 59883003 ps
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T310 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_aborted_low_power.4243601944 Aug 27 05:16:16 AM UTC 24 Aug 27 05:16:18 AM UTC 24 77019176 ps
T311 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_global_esc.1423636038 Aug 27 05:16:16 AM UTC 24 Aug 27 05:16:18 AM UTC 24 24981001 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.1704734346 Aug 27 05:16:16 AM UTC 24 Aug 27 05:16:18 AM UTC 24 77084872 ps
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T315 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_disable_rom_integrity_check.1790305758 Aug 27 05:16:16 AM UTC 24 Aug 27 05:16:18 AM UTC 24 56111447 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset_invalid.1061824684 Aug 27 05:16:16 AM UTC 24 Aug 27 05:16:18 AM UTC 24 254134205 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_26/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_smoke.3504886801 Aug 27 05:16:16 AM UTC 24 Aug 27 05:16:18 AM UTC 24 31835069 ps
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