Testbench Group List
dashboard | hierarchy | modlist | groups | tests | asserts
Total Groups Coverage Summary 
COVEREDEXPECTEDSCORECOVEREDEXPECTEDINST SCOREWEIGHT
603 611 98.69 603 611 98.69 1


Total groups in report: 25
NAMECOVEREDEXPECTEDSCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSINGCOMMENT
cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg 12 15 80.00 100.00 1 100 1 1 64 64
pwrmgr_env_pkg::pwrmgr_env_cov::rom_active_blockers_cg 22 24 91.67 1 100 1 0 64 64
cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg 13 14 92.86 100.00 1 100 1 1 64 64
alert_esc_agent_pkg::alert_handshake_complete_cg 3 3 100.00 100.00 1 100 1 1 64 64
alert_esc_agent_pkg::esc_handshake_complete_cg 3 3 100.00 100.00 1 100 1 1 64 64
cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=0} 9 9 100.00 1 100 1 0 64 64
cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=0} 9 9 100.00 1 100 1 0 64 64
cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=0} 13 13 100.00 1 100 1 0 64 64
dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg 2 2 100.00 78.57 1 100 1 1 64 64
dv_base_reg_pkg::mubi_cov#(4,32'b00000000000000000000000000000101,32'b00000000000000000000000000001010)::mubi_cg 6 6 100.00 100.00 1 100 1 1 64 64
dv_base_reg_pkg::mubi_cov#(4,32'h00000006,32'h00000009)::mubi_cg 6 6 100.00 100.00 1 100 1 1 64 64
dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg 4 4 100.00 100.00 1 100 1 1 64 64
tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if::prim_onehot_check_without_addr_fault_if_proxy::onehot_without_addr_fault_cg 2 2 100.00 100.00 1 100 1 1 64 64
pwrmgr_env_pkg::pwrmgr_env_cov::control_cg 76 76 100.00 1 100 1 0 64 64
pwrmgr_env_pkg::pwrmgr_env_cov::esc_reset_cg 7 7 100.00 1 100 1 0 64 64
pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_0_cg 12 12 100.00 1 100 1 0 64 64
pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_1_cg 12 12 100.00 1 100 1 0 64 64
pwrmgr_env_pkg::pwrmgr_env_cov::main_power_reset_cg 7 7 100.00 1 100 1 0 64 64
pwrmgr_env_pkg::pwrmgr_env_cov::reset_wakeup_distance_cg 9 9 100.00 1 100 1 0 64 64
pwrmgr_env_pkg::pwrmgr_env_cov::rstmgr_sw_reset_cg 2 2 100.00 1 100 1 0 64 64
pwrmgr_env_pkg::pwrmgr_wakeup_ctrl_cg_wrap::wakeup_ctrl_cg 14 14 100.00 100.00 1 100 1 1 64 64
pwrmgr_env_pkg::pwrmgr_wakeup_intr_cg_wrap::wakeup_intr_cg 16 16 100.00 100.00 1 100 1 1 64 64
tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=1} 1 1 100.00 100.00 1 100 1 1 64 64
tl_agent_pkg::pending_req_on_rst_cg 2 2 100.00 100.00 1 100 1 1 64 64
tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128} 137 137 100.00 100.00 1 100 1 1 64 64
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%