Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4959 |
1 |
|
|
T3 |
3 |
|
T4 |
8 |
|
T52 |
7 |
auto[1] |
14329 |
1 |
|
|
T1 |
1 |
|
T3 |
3 |
|
T4 |
10 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8735 |
1 |
|
|
T3 |
3 |
|
T4 |
10 |
|
T5 |
10 |
auto[1] |
10553 |
1 |
|
|
T1 |
1 |
|
T3 |
3 |
|
T4 |
8 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9076 |
1 |
|
|
T1 |
1 |
|
T3 |
2 |
|
T4 |
10 |
auto[1] |
10212 |
1 |
|
|
T3 |
4 |
|
T4 |
8 |
|
T5 |
6 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1105 |
1 |
|
|
T4 |
2 |
|
T52 |
3 |
|
T34 |
1 |
auto[0] |
auto[0] |
auto[1] |
1143 |
1 |
|
|
T3 |
1 |
|
T4 |
2 |
|
T52 |
1 |
auto[0] |
auto[1] |
auto[0] |
3383 |
1 |
|
|
T3 |
1 |
|
T4 |
4 |
|
T5 |
5 |
auto[0] |
auto[1] |
auto[1] |
3104 |
1 |
|
|
T3 |
1 |
|
T4 |
2 |
|
T5 |
5 |
auto[1] |
auto[0] |
auto[0] |
1127 |
1 |
|
|
T4 |
3 |
|
T52 |
2 |
|
T34 |
1 |
auto[1] |
auto[0] |
auto[1] |
1584 |
1 |
|
|
T3 |
2 |
|
T4 |
1 |
|
T52 |
1 |
auto[1] |
auto[1] |
auto[0] |
3461 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
auto[1] |
auto[1] |
auto[1] |
4381 |
1 |
|
|
T4 |
3 |
|
T5 |
1 |
|
T7 |
11 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4959 |
1 |
|
|
T3 |
3 |
|
T4 |
8 |
|
T52 |
7 |
auto[1] |
14329 |
1 |
|
|
T1 |
1 |
|
T3 |
3 |
|
T4 |
10 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8680 |
1 |
|
|
T3 |
3 |
|
T4 |
8 |
|
T5 |
5 |
auto[1] |
10608 |
1 |
|
|
T1 |
1 |
|
T3 |
3 |
|
T4 |
10 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9121 |
1 |
|
|
T3 |
1 |
|
T4 |
8 |
|
T5 |
4 |
auto[1] |
10167 |
1 |
|
|
T1 |
1 |
|
T3 |
5 |
|
T4 |
10 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1122 |
1 |
|
|
T3 |
1 |
|
T4 |
1 |
|
T52 |
2 |
auto[0] |
auto[0] |
auto[1] |
1147 |
1 |
|
|
T3 |
1 |
|
T4 |
3 |
|
T52 |
1 |
auto[0] |
auto[1] |
auto[0] |
3282 |
1 |
|
|
T4 |
4 |
|
T5 |
1 |
|
T7 |
8 |
auto[0] |
auto[1] |
auto[1] |
3129 |
1 |
|
|
T3 |
1 |
|
T5 |
4 |
|
T7 |
12 |
auto[1] |
auto[0] |
auto[0] |
1148 |
1 |
|
|
T4 |
2 |
|
T52 |
3 |
|
T34 |
3 |
auto[1] |
auto[0] |
auto[1] |
1542 |
1 |
|
|
T3 |
1 |
|
T4 |
2 |
|
T52 |
1 |
auto[1] |
auto[1] |
auto[0] |
3569 |
1 |
|
|
T4 |
1 |
|
T5 |
3 |
|
T7 |
12 |
auto[1] |
auto[1] |
auto[1] |
4349 |
1 |
|
|
T1 |
1 |
|
T3 |
2 |
|
T4 |
5 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4959 |
1 |
|
|
T3 |
3 |
|
T4 |
8 |
|
T52 |
7 |
auto[1] |
14329 |
1 |
|
|
T1 |
1 |
|
T3 |
3 |
|
T4 |
10 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8684 |
1 |
|
|
T3 |
3 |
|
T4 |
6 |
|
T5 |
6 |
auto[1] |
10604 |
1 |
|
|
T1 |
1 |
|
T3 |
3 |
|
T4 |
12 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9143 |
1 |
|
|
T1 |
1 |
|
T3 |
2 |
|
T4 |
8 |
auto[1] |
10145 |
1 |
|
|
T3 |
4 |
|
T4 |
10 |
|
T5 |
6 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1086 |
1 |
|
|
T3 |
2 |
|
T4 |
2 |
|
T52 |
1 |
auto[0] |
auto[0] |
auto[1] |
1153 |
1 |
|
|
T3 |
1 |
|
T4 |
1 |
|
T52 |
2 |
auto[0] |
auto[1] |
auto[0] |
3389 |
1 |
|
|
T4 |
2 |
|
T5 |
2 |
|
T7 |
10 |
auto[0] |
auto[1] |
auto[1] |
3056 |
1 |
|
|
T4 |
1 |
|
T5 |
4 |
|
T7 |
13 |
auto[1] |
auto[0] |
auto[0] |
1152 |
1 |
|
|
T4 |
1 |
|
T52 |
1 |
|
T34 |
2 |
auto[1] |
auto[0] |
auto[1] |
1568 |
1 |
|
|
T4 |
4 |
|
T52 |
3 |
|
T34 |
3 |
auto[1] |
auto[1] |
auto[0] |
3516 |
1 |
|
|
T1 |
1 |
|
T4 |
3 |
|
T5 |
3 |
auto[1] |
auto[1] |
auto[1] |
4368 |
1 |
|
|
T3 |
3 |
|
T4 |
4 |
|
T5 |
2 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4959 |
1 |
|
|
T3 |
3 |
|
T4 |
8 |
|
T52 |
7 |
auto[1] |
14329 |
1 |
|
|
T1 |
1 |
|
T3 |
3 |
|
T4 |
10 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8775 |
1 |
|
|
T3 |
3 |
|
T4 |
10 |
|
T5 |
2 |
auto[1] |
10513 |
1 |
|
|
T1 |
1 |
|
T3 |
3 |
|
T4 |
8 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9136 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
10 |
auto[1] |
10152 |
1 |
|
|
T3 |
5 |
|
T4 |
8 |
|
T5 |
8 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1130 |
1 |
|
|
T4 |
2 |
|
T52 |
1 |
|
T34 |
5 |
auto[0] |
auto[0] |
auto[1] |
1154 |
1 |
|
|
T3 |
2 |
|
T4 |
2 |
|
T52 |
1 |
auto[0] |
auto[1] |
auto[0] |
3393 |
1 |
|
|
T4 |
4 |
|
T5 |
1 |
|
T7 |
16 |
auto[0] |
auto[1] |
auto[1] |
3098 |
1 |
|
|
T3 |
1 |
|
T4 |
2 |
|
T5 |
1 |
auto[1] |
auto[0] |
auto[0] |
1146 |
1 |
|
|
T3 |
1 |
|
T4 |
1 |
|
T52 |
1 |
auto[1] |
auto[0] |
auto[1] |
1529 |
1 |
|
|
T4 |
3 |
|
T52 |
4 |
|
T34 |
2 |
auto[1] |
auto[1] |
auto[0] |
3467 |
1 |
|
|
T1 |
1 |
|
T4 |
3 |
|
T5 |
2 |
auto[1] |
auto[1] |
auto[1] |
4371 |
1 |
|
|
T3 |
2 |
|
T4 |
1 |
|
T5 |
7 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4959 |
1 |
|
|
T3 |
3 |
|
T4 |
8 |
|
T52 |
7 |
auto[1] |
14329 |
1 |
|
|
T1 |
1 |
|
T3 |
3 |
|
T4 |
10 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8616 |
1 |
|
|
T3 |
3 |
|
T4 |
7 |
|
T5 |
8 |
auto[1] |
10672 |
1 |
|
|
T1 |
1 |
|
T3 |
3 |
|
T4 |
11 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8947 |
1 |
|
|
T3 |
2 |
|
T4 |
7 |
|
T5 |
6 |
auto[1] |
10341 |
1 |
|
|
T1 |
1 |
|
T3 |
4 |
|
T4 |
11 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1084 |
1 |
|
|
T3 |
1 |
|
T4 |
1 |
|
T52 |
2 |
auto[0] |
auto[0] |
auto[1] |
1223 |
1 |
|
|
T3 |
1 |
|
T4 |
1 |
|
T52 |
2 |
auto[0] |
auto[1] |
auto[0] |
3312 |
1 |
|
|
T4 |
2 |
|
T5 |
4 |
|
T7 |
16 |
auto[0] |
auto[1] |
auto[1] |
2997 |
1 |
|
|
T3 |
1 |
|
T4 |
3 |
|
T5 |
4 |
auto[1] |
auto[0] |
auto[0] |
1052 |
1 |
|
|
T4 |
1 |
|
T52 |
2 |
|
T34 |
2 |
auto[1] |
auto[0] |
auto[1] |
1600 |
1 |
|
|
T3 |
1 |
|
T4 |
5 |
|
T52 |
1 |
auto[1] |
auto[1] |
auto[0] |
3499 |
1 |
|
|
T3 |
1 |
|
T4 |
3 |
|
T5 |
2 |
auto[1] |
auto[1] |
auto[1] |
4521 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
2 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4959 |
1 |
|
|
T3 |
3 |
|
T4 |
8 |
|
T52 |
7 |
auto[1] |
14329 |
1 |
|
|
T1 |
1 |
|
T3 |
3 |
|
T4 |
10 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8681 |
1 |
|
|
T3 |
3 |
|
T4 |
12 |
|
T5 |
4 |
auto[1] |
10607 |
1 |
|
|
T1 |
1 |
|
T3 |
3 |
|
T4 |
6 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9110 |
1 |
|
|
T4 |
6 |
|
T5 |
7 |
|
T7 |
19 |
auto[1] |
10178 |
1 |
|
|
T1 |
1 |
|
T3 |
6 |
|
T4 |
12 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1062 |
1 |
|
|
T4 |
1 |
|
T52 |
2 |
|
T34 |
5 |
auto[0] |
auto[0] |
auto[1] |
1218 |
1 |
|
|
T3 |
2 |
|
T4 |
3 |
|
T52 |
3 |
auto[0] |
auto[1] |
auto[0] |
3317 |
1 |
|
|
T4 |
1 |
|
T5 |
2 |
|
T7 |
7 |
auto[0] |
auto[1] |
auto[1] |
3084 |
1 |
|
|
T3 |
1 |
|
T4 |
7 |
|
T5 |
2 |
auto[1] |
auto[0] |
auto[0] |
1168 |
1 |
|
|
T4 |
3 |
|
T52 |
1 |
|
T36 |
4 |
auto[1] |
auto[0] |
auto[1] |
1511 |
1 |
|
|
T3 |
1 |
|
T4 |
1 |
|
T52 |
1 |
auto[1] |
auto[1] |
auto[0] |
3563 |
1 |
|
|
T4 |
1 |
|
T5 |
5 |
|
T7 |
12 |
auto[1] |
auto[1] |
auto[1] |
4365 |
1 |
|
|
T1 |
1 |
|
T3 |
2 |
|
T4 |
1 |