Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	374196	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

147452

1

T1

11

T2

19

T3

36

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	273074	1			T1	18		T2	62		T3	53
values[0x0]	124328	1			T1	8		T2	15		T3	28
values[0x1]	124246	1			T1	2		T2	23		T3	14

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	296341	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

225307

1

T1

14

T2

37

T3

45

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1663	1			T34	3		T15	1		T35	1
valid_sources[0x01]	1656	1			T33	1		T34	1		T39	3
valid_sources[0x02]	1954	1			T3	1		T9	11		T33	2
valid_sources[0x03]	1992	1			T34	1		T37	3		T39	1
valid_sources[0x04]	1922	1			T5	2		T29	2		T34	4
valid_sources[0x05]	1873	1			T5	13		T9	11		T33	1
valid_sources[0x06]	1534	1			T14	4		T33	2		T34	1
valid_sources[0x07]	4315	1			T4	7		T5	1		T9	14
valid_sources[0x08]	1667	1			T2	1		T5	1		T34	1
valid_sources[0x09]	1647	1			T5	2		T9	7		T33	1
valid_sources[0x0a]	1419	1			T5	1		T34	1		T15	3
valid_sources[0x0b]	1679	1			T3	1		T29	1		T28	10
valid_sources[0x0c]	1566	1			T9	8		T34	2		T12	1
valid_sources[0x0d]	2013	1			T2	1		T9	26		T20	3
valid_sources[0x0e]	2293	1			T29	1		T39	2		T28	8
valid_sources[0x0f]	1918	1			T34	2		T35	1		T39	1
valid_sources[0x10]	1579	1			T1	7		T2	2		T29	3
valid_sources[0x11]	1741	1			T2	1		T5	1		T29	1
valid_sources[0x12]	1408	1			T2	1		T32	2		T39	14
valid_sources[0x13]	2303	1			T3	1		T4	1		T7	857
valid_sources[0x14]	1594	1			T29	1		T28	14		T42	1
valid_sources[0x15]	2304	1			T2	1		T6	35		T9	16
valid_sources[0x16]	1622	1			T4	1		T5	3		T9	10
valid_sources[0x17]	1531	1			T36	12		T39	2		T42	1
valid_sources[0x18]	2668	1			T29	1		T33	1		T35	5
valid_sources[0x19]	1834	1			T4	2		T52	180		T29	1
valid_sources[0x1a]	1776	1			T2	1		T32	1		T35	4
valid_sources[0x1b]	2057	1			T29	1		T34	1		T36	6
valid_sources[0x1c]	1570	1			T3	1		T4	2		T5	5
valid_sources[0x1d]	4897	1			T3	2		T4	3		T33	1
valid_sources[0x1e]	2014	1			T33	1		T34	5		T39	12
valid_sources[0x1f]	2237	1			T9	9		T14	11		T33	1
valid_sources[0x20]	2177	1			T3	1		T33	2		T34	1
valid_sources[0x21]	1580	1			T35	1		T39	9		T42	1
valid_sources[0x22]	1739	1			T2	1		T9	2		T20	1
valid_sources[0x23]	1532	1			T5	1		T14	8		T29	1
valid_sources[0x24]	2127	1			T3	1		T4	3		T32	1
valid_sources[0x25]	1766	1			T5	2		T34	1		T39	3
valid_sources[0x26]	2526	1			T2	1		T9	13		T29	1
valid_sources[0x27]	2735	1			T9	2		T29	1		T35	4
valid_sources[0x28]	1434	1			T3	1		T33	1		T34	1
valid_sources[0x29]	1710	1			T2	1		T6	16		T33	1
valid_sources[0x2a]	2006	1			T43	3		T33	1		T35	1
valid_sources[0x2b]	1695	1			T4	1		T9	8		T29	1
valid_sources[0x2c]	1343	1			T2	1		T3	1		T4	1
valid_sources[0x2d]	2497	1			T33	1		T15	1		T35	1
valid_sources[0x2e]	1726	1			T34	4		T35	6		T39	1
valid_sources[0x2f]	1776	1			T4	3		T33	1		T34	1
valid_sources[0x30]	1438	1			T4	5		T5	4		T33	1
valid_sources[0x31]	2502	1			T5	4		T33	1		T34	1
valid_sources[0x32]	1611	1			T5	2		T33	1		T39	8
valid_sources[0x33]	2585	1			T5	1		T9	2		T33	1
valid_sources[0x34]	1737	1			T9	14		T33	1		T34	1
valid_sources[0x35]	1697	1			T3	1		T4	1		T14	1
valid_sources[0x36]	1725	1			T4	5		T14	2		T29	1
valid_sources[0x37]	1625	1			T34	1		T15	3		T39	1
valid_sources[0x38]	2857	1			T9	2		T34	1		T15	1
valid_sources[0x39]	2089	1			T2	1		T4	4		T34	1
valid_sources[0x3a]	2606	1			T5	3		T29	1		T33	2
valid_sources[0x3b]	1494	1			T2	2		T4	1		T33	3
valid_sources[0x3c]	1513	1			T33	5		T34	1		T35	4
valid_sources[0x3d]	1869	1			T2	2		T29	2		T34	2
valid_sources[0x3e]	9717	1			T3	1		T4	3		T5	3
valid_sources[0x3f]	1631	1			T2	1		T9	51		T32	3
valid_sources[0x40]	1714	1			T3	1		T5	1		T33	2
valid_sources[0x41]	2146	1			T4	2		T5	1		T39	2
valid_sources[0x42]	1694	1			T6	19		T34	1		T15	1
valid_sources[0x43]	1615	1			T4	3		T5	3		T35	1
valid_sources[0x44]	2311	1			T29	1		T15	2		T35	5
valid_sources[0x45]	1625	1			T33	2		T39	8		T28	1
valid_sources[0x46]	2370	1			T33	3		T34	1		T36	7
valid_sources[0x47]	2092	1			T2	2		T3	1		T4	1
valid_sources[0x48]	2254	1			T2	2		T3	1		T5	1
valid_sources[0x49]	1567	1			T4	8		T5	4		T34	4
valid_sources[0x4a]	1583	1			T5	1		T29	2		T33	2
valid_sources[0x4b]	2512	1			T4	6		T5	3		T29	1
valid_sources[0x4c]	2178	1			T33	2		T34	1		T36	2
valid_sources[0x4d]	1736	1			T2	2		T5	5		T29	1
valid_sources[0x4e]	1674	1			T2	3		T39	1		T41	12
valid_sources[0x4f]	1476	1			T2	1		T3	1		T4	3
valid_sources[0x50]	1765	1			T3	2		T4	1		T33	1
valid_sources[0x51]	1385	1			T33	1		T39	1		T42	1
valid_sources[0x52]	1561	1			T2	1		T3	1		T9	1
valid_sources[0x53]	1936	1			T29	1		T34	3		T36	12
valid_sources[0x54]	2156	1			T29	1		T32	1		T33	1
valid_sources[0x55]	1670	1			T4	1		T29	1		T34	1
valid_sources[0x56]	1604	1			T2	1		T3	1		T15	2
valid_sources[0x57]	1642	1			T3	3		T15	4		T35	3
valid_sources[0x58]	1483	1			T3	1		T9	16		T34	1
valid_sources[0x59]	2318	1			T2	1		T5	1		T29	2
valid_sources[0x5a]	2098	1			T4	7		T33	1		T35	2
valid_sources[0x5b]	4177	1			T9	1		T34	1		T15	1
valid_sources[0x5c]	1674	1			T29	1		T35	2		T39	2
valid_sources[0x5d]	2347	1			T29	1		T33	2		T15	2
valid_sources[0x5e]	2227	1			T2	1		T33	1		T35	4
valid_sources[0x5f]	1874	1			T4	1		T5	1		T6	6
valid_sources[0x60]	2072	1			T1	20		T4	3		T9	25
valid_sources[0x61]	2206	1			T2	1		T3	2		T43	3
valid_sources[0x62]	2301	1			T2	2		T3	1		T29	1
valid_sources[0x63]	1592	1			T6	5		T33	2		T34	1
valid_sources[0x64]	3367	1			T29	1		T33	1		T35	2
valid_sources[0x65]	1664	1			T9	1		T33	1		T34	1
valid_sources[0x66]	2251	1			T3	2		T5	1		T9	9
valid_sources[0x67]	2763	1			T33	2		T15	1		T37	2
valid_sources[0x68]	1874	1			T5	2		T34	4		T35	1
valid_sources[0x69]	1787	1			T29	2		T33	1		T34	2
valid_sources[0x6a]	1682	1			T2	1		T9	9		T34	1
valid_sources[0x6b]	1408	1			T5	1		T9	11		T29	1
valid_sources[0x6c]	1891	1			T2	1		T9	21		T14	6
valid_sources[0x6d]	1599	1			T23	1		T29	2		T35	4
valid_sources[0x6e]	1824	1			T3	2		T5	2		T33	1
valid_sources[0x6f]	1759	1			T3	1		T5	3		T8	244
valid_sources[0x70]	1904	1			T29	2		T34	1		T35	1
valid_sources[0x71]	1747	1			T2	1		T33	2		T15	2
valid_sources[0x72]	1652	1			T4	1		T29	1		T33	1
valid_sources[0x73]	4007	1			T4	1		T5	1		T29	1
valid_sources[0x74]	1805	1			T29	1		T34	2		T39	4
valid_sources[0x75]	1462	1			T2	2		T28	4		T42	1
valid_sources[0x76]	1730	1			T5	3		T33	1		T34	1
valid_sources[0x77]	1740	1			T4	1		T9	6		T34	1
valid_sources[0x78]	1839	1			T2	2		T3	2		T4	9
valid_sources[0x79]	2396	1			T3	1		T5	1		T29	2
valid_sources[0x7a]	1562	1			T3	1		T5	2		T9	9
valid_sources[0x7b]	1780	1			T3	1		T15	3		T36	9
valid_sources[0x7c]	1689	1			T3	4		T29	1		T34	2
valid_sources[0x7d]	1632	1			T3	2		T5	3		T9	13
valid_sources[0x7e]	2442	1			T2	3		T29	1		T35	1
valid_sources[0x7f]	3333	1			T2	1		T29	2		T33	3
valid_sources[0x80]	4754	1			T3	1		T5	3		T32	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

74092

1

T1

7

T2

11

T3

20

values[0x0]

all_enables

biggest_size

47152

1

T1

3

T2

5

T3

14

values[0x1]

all_enables

biggest_size

26208

1

T1

1

T2

3

T3

2