SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 32324 | 1 | T7 | 308 | T9 | 390 | T39 | 385 | ||||
others[1] | 32603 | 1 | T7 | 308 | T9 | 408 | T39 | 424 | ||||
others[2] | 32777 | 1 | T7 | 270 | T9 | 404 | T39 | 386 | ||||
others[3] | 54610 | 1 | T7 | 509 | T9 | 675 | T27 | 1 | ||||
false | 13288 | 1 | T5 | 22 | T7 | 50 | T9 | 50 | ||||
true | 21796 | 1 | T1 | 1 | T2 | 2 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 32974 | 1 | T7 | 296 | T9 | 408 | T14 | 1 | ||||
others[1] | 32595 | 1 | T7 | 305 | T9 | 378 | T14 | 1 | ||||
others[2] | 32393 | 1 | T7 | 309 | T9 | 424 | T39 | 400 | ||||
others[3] | 54327 | 1 | T7 | 495 | T9 | 657 | T39 | 630 | ||||
false | 9085 | 1 | T5 | 11 | T7 | 50 | T9 | 50 | ||||
true | 17622 | 1 | T1 | 1 | T2 | 2 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 572 | 1 | T2 | 1 | T8 | 3 | T37 | 4 | ||||
others[1] | 566 | 1 | T2 | 1 | T8 | 3 | T33 | 1 | ||||
others[2] | 597 | 1 | T8 | 7 | T29 | 1 | T33 | 2 | ||||
others[3] | 958 | 1 | T2 | 1 | T8 | 12 | T29 | 2 | ||||
false | 10865 | 1 | T1 | 1 | T2 | 10 | T3 | 1 | ||||
true | 3068 | 1 | T2 | 5 | T8 | 4 | T14 | 5 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |