Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24090

1

T1

2

T3

2

T4

8

auto[1]

22836

1

T3

4

T4

10

T5

3

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24000

1

T1

2

T3

4

T4

6

auto[1]

22926

1

T3

2

T4

12

T5

5

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23129

1

T3

6

T4

8

T5

3

auto[1]

23797

1

T1

2

T4

10

T5

5

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26280

1

T1

1

T3

3

T4

9

auto[1]

20646

1

T1

1

T3

3

T4

9

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22964

1

T3

2

T4

8

T5

5

auto[1]

23962

1

T1

2

T3

4

T4

10

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24070

1

T1

2

T3

2

T4

6

auto[1]

22856

1

T3

4

T4

12

T5

8

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

837

1

T6

1

T10

2

T14

4

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

664

1

T6

1

T10

2

T14

4

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

825

1

T10

3

T23

2

T33

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

655

1

T10

3

T23

1

T33

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

796

1

T3

1

T16

6

T57

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

612

1

T3

1

T16

4

T24

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1293

1

T1

1

T10

5

T23

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1119

1

T1

1

T10

5

T14

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

803

1

T6

2

T23

1

T14

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

631

1

T6

2

T23

1

T14

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

851

1

T14

2

T34

1

T35

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

681

1

T14

2

T34

1

T35

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

812

1

T10

1

T14

2

T15

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

653

1

T10

1

T14

2

T35

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

776

1

T5

1

T10

1

T14

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

603

1

T10

1

T14

2

T16

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

816

1

T10

3

T23

2

T14

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

649

1

T10

3

T23

1

T14

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

804

1

T10

3

T14

1

T41

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

626

1

T10

3

T14

1

T16

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

861

1

T10

4

T23

1

T14

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

670

1

T10

4

T14

2

T35

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

826

1

T4

1

T10

1

T23

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

627

1

T4

1

T10

1

T16

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

804

1

T4

1

T5

1

T10

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

626

1

T4

1

T10

1

T23

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

789

1

T5

2

T23

1

T14

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

577

1

T14

2

T34

1

T35

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

786

1

T4

2

T5

1

T6

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

618

1

T4

2

T6

1

T10

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

792

1

T23

1

T14

4

T15

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

608

1

T23

1

T14

4

T16

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

785

1

T4

1

T6

2

T10

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

620

1

T4

1

T6

2

T10

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

758

1

T4

1

T10

5

T14

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

593

1

T4

1

T10

5

T14

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

829

1

T10

1

T14

1

T34

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

650

1

T10

1

T14

1

T34

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

813

1

T10

1

T23

1

T14

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

636

1

T10

1

T23

1

T14

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

805

1

T6

2

T10

2

T34

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

633

1

T6

2

T10

2

T34

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

773

1

T5

1

T10

1

T14

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

616

1

T10

1

T14

1

T35

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

832

1

T3

1

T10

2

T23

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

651

1

T3

1

T10

2

T23

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

792

1

T4

1

T5

1

T10

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

603

1

T4

1

T10

1

T14

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

807

1

T6

2

T10

2

T23

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

633

1

T6

2

T10

2

T41

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

814

1

T6

2

T10

1

T14

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

621

1

T6

2

T10

1

T14

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

782

1

T14

2

T35

1

T16

6

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

609

1

T14

2

T35

1

T16

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

815

1

T6

1

T10

2

T23

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

625

1

T6

1

T10

2

T23

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

784

1

T3

1

T5

1

T10

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

632

1

T3

1

T10

1

T14

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

811

1

T4

1

T10

1

T23

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

641

1

T4

1

T10

1

T34

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

802

1

T6

1

T23

1

T14

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

637

1

T6

1

T14

2

T27

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

807

1

T4

1

T10

4

T23

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

627

1

T4

1

T10

4

T14

1