Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 98.23 96.58 99.62 96.00 96.37 100.00 98.85


Total tests in report: 1080
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
79.27 79.27 95.74 95.74 79.03 79.03 62.62 62.62 60.00 60.00 92.56 92.56 91.32 91.32 73.65 73.65 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4250778048
85.82 6.55 96.06 0.32 86.73 7.70 94.07 31.45 62.00 2.00 93.89 1.34 93.68 2.37 74.30 0.65 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm.1294712970
89.64 3.81 96.31 0.24 86.73 0.00 96.70 2.64 84.00 22.00 94.08 0.19 93.68 0.00 75.94 1.64 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset_invalid.194374049
92.25 2.61 97.03 0.72 89.16 2.43 97.36 0.66 88.00 4.00 94.66 0.57 93.95 0.26 85.60 9.66 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all_with_rand_reset.3831598113
93.52 1.27 97.03 0.00 89.16 0.00 98.12 0.75 96.00 8.00 94.66 0.00 93.95 0.00 85.76 0.16 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_invalid.3814825918
94.71 1.18 97.75 0.72 92.01 2.85 98.31 0.19 96.00 0.00 95.42 0.76 93.95 0.00 89.53 3.76 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.2205661011
95.74 1.03 97.83 0.08 93.30 1.28 98.68 0.38 96.00 0.00 95.61 0.19 95.00 1.05 93.78 4.26 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all_with_rand_reset.1632242470
96.08 0.34 98.07 0.24 93.44 0.14 98.68 0.00 96.00 0.00 95.61 0.00 95.00 0.00 95.74 1.96 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_intr_test.40349534
96.37 0.29 98.07 0.00 93.72 0.29 99.62 0.94 96.00 0.00 95.80 0.19 95.26 0.26 96.07 0.33 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3309563675
96.63 0.27 98.07 0.00 95.44 1.71 99.62 0.00 96.00 0.00 95.80 0.00 95.26 0.00 96.24 0.16 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_errors.3735279641
96.90 0.26 98.07 0.00 95.44 0.00 99.62 0.00 96.00 0.00 95.80 0.00 97.11 1.84 96.24 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_rw.4255258077
97.14 0.24 98.23 0.16 95.86 0.43 99.62 0.00 96.00 0.00 96.37 0.57 97.63 0.53 96.24 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.753130724
97.36 0.22 98.23 0.00 96.01 0.14 99.62 0.00 96.00 0.00 96.37 0.00 97.89 0.26 97.38 1.15 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.4037070056
97.57 0.21 98.23 0.00 96.15 0.14 99.62 0.00 96.00 0.00 96.37 0.00 99.21 1.32 97.38 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_stress_all_with_rand_reset.3293108598
97.64 0.08 98.23 0.00 96.15 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.53 97.38 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_aborted_low_power.3391586564
97.71 0.07 98.23 0.00 96.15 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.00 97.87 0.49 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_disable_rom_integrity_check.3489637983
97.78 0.07 98.23 0.00 96.29 0.14 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.00 98.20 0.33 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.3705617552
97.83 0.05 98.23 0.00 96.29 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.00 98.53 0.33 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_disable_rom_integrity_check.3784493266
97.85 0.02 98.23 0.00 96.29 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.00 98.69 0.16 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_intr_test.1848359481
97.87 0.02 98.23 0.00 96.29 0.00 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.00 98.85 0.16 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_disable_rom_integrity_check.3670721803
97.89 0.02 98.23 0.00 96.43 0.14 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.00 98.85 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.2491689750
97.91 0.02 98.23 0.00 96.58 0.14 99.62 0.00 96.00 0.00 96.37 0.00 99.74 0.00 98.85 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_glitch.3164715124

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_errors.3064938779
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.1941325196
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.2164646088
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.654686618
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_rw.3977017047
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.1107451561
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.1618261843
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_rw.3748015531
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_intr_test.1145134814
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.735971007
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_errors.2663688627
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.808264017
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.3400049533
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_rw.3982207139
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.3028739600
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_errors.2753784374
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.673456903
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.886913700
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_rw.2375033053
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_intr_test.3493462811
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.2013652010
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_errors.3840942624
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.911204028
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.3399272284
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_rw.1652310875
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_intr_test.1110993669
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.85734336
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_errors.2606492961
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.2326996259
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.1050535563
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_rw.1591009331
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_intr_test.497673063
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.965559390
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_errors.1441796100
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.1711332134
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_rw.3005735091
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_intr_test.4186470623
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.520602349
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_errors.3753956001
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.2709502153
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.1226201768
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_rw.1741956966
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_intr_test.1762781804
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.1524505388
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_errors.4120974604
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.3415183102
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_rw.1781372735
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_intr_test.2764396
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.4185484725
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_errors.1730181701
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.3306786568
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.3194226826
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_rw.87573381
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_intr_test.2869580077
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.1537317805
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_errors.1640240792
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.3803710771
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.4091848959
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_rw.1488498465
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_intr_test.1579476807
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.1162834201
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_errors.2167257003
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.2902755435
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.740674342
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/20.pwrmgr_intr_test.1311725664
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/21.pwrmgr_intr_test.475958309
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/22.pwrmgr_intr_test.679305173
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/23.pwrmgr_intr_test.2821652588
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/24.pwrmgr_intr_test.1528775893
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/25.pwrmgr_intr_test.732806608
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/26.pwrmgr_intr_test.1906655404
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/27.pwrmgr_intr_test.252440339
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/28.pwrmgr_intr_test.4293035372
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/29.pwrmgr_intr_test.647756254
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.2959507766
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.1245609657
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_rw.1780777374
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/30.pwrmgr_intr_test.445483489
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/31.pwrmgr_intr_test.3205853020
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/32.pwrmgr_intr_test.3600195793
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/33.pwrmgr_intr_test.3501094871
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/34.pwrmgr_intr_test.1793657
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/35.pwrmgr_intr_test.2325733279
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/36.pwrmgr_intr_test.803525519
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/37.pwrmgr_intr_test.2649911313
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/38.pwrmgr_intr_test.3003357226
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/39.pwrmgr_intr_test.2490428017
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.1733441286
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.2770273226
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.2677439892
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.3551714152
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_intr_test.3599538998
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.2828893679
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_errors.3938328809
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.3374792375
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/40.pwrmgr_intr_test.3331603592
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/41.pwrmgr_intr_test.4088310855
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/cover_reg_top/42.pwrmgr_intr_test.3488414615
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/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_aborted_low_power.3549509202
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_disable_rom_integrity_check.2652940876
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.2119386660
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_escalation_timeout.711823315
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_glitch.1494783797
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_global_esc.3498514481
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_invalid.3961992286
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_wakeup_race.347765679
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset.1827902665
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset_invalid.2595646680
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.86778077
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2696942967
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.940926999
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.301257808
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_smoke.354105454
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all.194739361
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all_with_rand_reset.1793581344
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup.3878815143
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup_reset.1282468930
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_aborted_low_power.1691462706
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_disable_rom_integrity_check.1707803940
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.2879382215
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_escalation_timeout.2723881886
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_glitch.2842535226
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_global_esc.2254552787
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_invalid.3034082143
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_wakeup_race.823586089
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset.711111700
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset_invalid.2399056906
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.2758150890
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2369915750
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.358549592
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.2998765203
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_smoke.2483281390
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all.3833286437
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all_with_rand_reset.3318991635
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup.4064615462
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup_reset.3946665729
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_aborted_low_power.2036490079
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_disable_rom_integrity_check.4006414670
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.1577581160
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_escalation_timeout.1346470598
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_glitch.2820672817
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_global_esc.3108086525
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_invalid.731680045
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_wakeup_race.856733036
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset.4051387057
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset_invalid.2076483937
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.706742983
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2265132932
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3376376545
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.3957909498
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_smoke.276251561
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all.1629594353
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup.593490288
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup_reset.80726172
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_aborted_low_power.2036421519
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_disable_rom_integrity_check.2190199376
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.2210572453
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_escalation_timeout.3465327462
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_glitch.315184486
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_global_esc.3035199393
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_invalid.666789350
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_wakeup_race.1820127380
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset.2882392979
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset_invalid.4189521796
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.1117195714
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.911985115
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.679925430
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.3855133263
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_smoke.716372783
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all.888662113
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all_with_rand_reset.1031212406
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup.1450389063
/workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup_reset.2777896967



Total test records in report: 1080
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_smoke.2967656978 Sep 01 08:24:29 PM UTC 24 Sep 01 08:24:31 PM UTC 24 31150532 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset.4292651962 Sep 01 08:24:30 PM UTC 24 Sep 01 08:24:32 PM UTC 24 74115574 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup_reset.656296410 Sep 01 08:24:32 PM UTC 24 Sep 01 08:24:34 PM UTC 24 85433227 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_wakeup_race.835856659 Sep 01 08:24:32 PM UTC 24 Sep 01 08:24:34 PM UTC 24 354848703 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_aborted_low_power.3391586564 Sep 01 08:24:32 PM UTC 24 Sep 01 08:24:34 PM UTC 24 30684182 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup.4140272968 Sep 01 08:24:32 PM UTC 24 Sep 01 08:24:34 PM UTC 24 272411770 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.753130724 Sep 01 08:24:35 PM UTC 24 Sep 01 08:24:37 PM UTC 24 35910382 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_global_esc.2496699572 Sep 01 08:24:35 PM UTC 24 Sep 01 08:24:38 PM UTC 24 90161855 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.2550125054 Sep 01 08:24:35 PM UTC 24 Sep 01 08:24:38 PM UTC 24 80678323 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4250778048 Sep 01 08:24:33 PM UTC 24 Sep 01 08:24:38 PM UTC 24 1093100532 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.2223104764 Sep 01 08:24:35 PM UTC 24 Sep 01 08:24:38 PM UTC 24 148254519 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_escalation_timeout.1664949590 Sep 01 08:24:37 PM UTC 24 Sep 01 08:24:40 PM UTC 24 108128830 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_glitch.3164715124 Sep 01 08:24:38 PM UTC 24 Sep 01 08:24:40 PM UTC 24 47693940 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4060006514 Sep 01 08:24:35 PM UTC 24 Sep 01 08:24:40 PM UTC 24 1120010559 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_disable_rom_integrity_check.2461185171 Sep 01 08:24:39 PM UTC 24 Sep 01 08:24:41 PM UTC 24 97026596 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_invalid.3814825918 Sep 01 08:24:39 PM UTC 24 Sep 01 08:24:41 PM UTC 24 42242178 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset_invalid.194374049 Sep 01 08:24:39 PM UTC 24 Sep 01 08:24:41 PM UTC 24 210708015 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm.1294712970 Sep 01 08:24:39 PM UTC 24 Sep 01 08:24:42 PM UTC 24 1329804804 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset.3112645509 Sep 01 08:24:41 PM UTC 24 Sep 01 08:24:43 PM UTC 24 38458175 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_smoke.1238705602 Sep 01 08:24:41 PM UTC 24 Sep 01 08:24:43 PM UTC 24 42698069 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup.1207129278 Sep 01 08:24:41 PM UTC 24 Sep 01 08:24:43 PM UTC 24 196069576 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_wakeup_race.2799721953 Sep 01 08:24:41 PM UTC 24 Sep 01 08:24:44 PM UTC 24 236101658 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_aborted_low_power.1625249215 Sep 01 08:24:42 PM UTC 24 Sep 01 08:24:45 PM UTC 24 65573683 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup_reset.2525304481 Sep 01 08:24:42 PM UTC 24 Sep 01 08:24:45 PM UTC 24 206927877 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.2077891767 Sep 01 08:24:44 PM UTC 24 Sep 01 08:24:46 PM UTC 24 29529451 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.86171929 Sep 01 08:24:44 PM UTC 24 Sep 01 08:24:46 PM UTC 24 65064563 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all.3944538894 Sep 01 08:24:41 PM UTC 24 Sep 01 08:24:46 PM UTC 24 2151389532 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.4037070056 Sep 01 08:24:45 PM UTC 24 Sep 01 08:24:47 PM UTC 24 269546297 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3836964823 Sep 01 08:24:44 PM UTC 24 Sep 01 08:24:48 PM UTC 24 997784458 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all_with_rand_reset.3831598113 Sep 01 08:24:39 PM UTC 24 Sep 01 08:24:48 PM UTC 24 2805308810 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_global_esc.2310454806 Sep 01 08:24:46 PM UTC 24 Sep 01 08:24:48 PM UTC 24 28835447 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_glitch.3204889738 Sep 01 08:24:46 PM UTC 24 Sep 01 08:24:48 PM UTC 24 38569524 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_escalation_timeout.712472397 Sep 01 08:24:46 PM UTC 24 Sep 01 08:24:48 PM UTC 24 380343111 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_disable_rom_integrity_check.3049294884 Sep 01 08:24:47 PM UTC 24 Sep 01 08:24:49 PM UTC 24 71968504 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_invalid.1518545930 Sep 01 08:24:47 PM UTC 24 Sep 01 08:24:49 PM UTC 24 55368336 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset_invalid.1868515211 Sep 01 08:24:47 PM UTC 24 Sep 01 08:24:50 PM UTC 24 136413867 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1068750621 Sep 01 08:24:44 PM UTC 24 Sep 01 08:24:50 PM UTC 24 871997832 ps
T139 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_smoke.3930932377 Sep 01 08:24:49 PM UTC 24 Sep 01 08:24:51 PM UTC 24 26569953 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset.329530266 Sep 01 08:24:49 PM UTC 24 Sep 01 08:24:51 PM UTC 24 80650537 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm.3842880720 Sep 01 08:24:49 PM UTC 24 Sep 01 08:24:51 PM UTC 24 464821880 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup.665069684 Sep 01 08:24:49 PM UTC 24 Sep 01 08:24:51 PM UTC 24 114701619 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_wakeup_race.2048806231 Sep 01 08:24:49 PM UTC 24 Sep 01 08:24:52 PM UTC 24 291644531 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup_reset.110108540 Sep 01 08:24:50 PM UTC 24 Sep 01 08:24:52 PM UTC 24 55217283 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_aborted_low_power.810989523 Sep 01 08:24:50 PM UTC 24 Sep 01 08:24:53 PM UTC 24 33797608 ps
T130 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all.3199449136 Sep 01 08:24:49 PM UTC 24 Sep 01 08:24:53 PM UTC 24 401579962 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.2223154699 Sep 01 08:24:51 PM UTC 24 Sep 01 08:24:53 PM UTC 24 29347503 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.1978266511 Sep 01 08:24:52 PM UTC 24 Sep 01 08:24:54 PM UTC 24 314130351 ps
T140 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.576130296 Sep 01 08:24:51 PM UTC 24 Sep 01 08:24:54 PM UTC 24 107060740 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.582140677 Sep 01 08:24:50 PM UTC 24 Sep 01 08:24:55 PM UTC 24 2357184808 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_global_esc.3244699684 Sep 01 08:24:53 PM UTC 24 Sep 01 08:24:55 PM UTC 24 25732915 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_glitch.3878624040 Sep 01 08:24:53 PM UTC 24 Sep 01 08:24:55 PM UTC 24 46471994 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_disable_rom_integrity_check.3489637983 Sep 01 08:24:53 PM UTC 24 Sep 01 08:24:55 PM UTC 24 89616125 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_escalation_timeout.2412675692 Sep 01 08:24:53 PM UTC 24 Sep 01 08:24:55 PM UTC 24 400308790 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset_invalid.1319618463 Sep 01 08:24:53 PM UTC 24 Sep 01 08:24:55 PM UTC 24 111853014 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_invalid.3350414290 Sep 01 08:24:54 PM UTC 24 Sep 01 08:24:56 PM UTC 24 228000275 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2913429845 Sep 01 08:24:50 PM UTC 24 Sep 01 08:24:56 PM UTC 24 841763465 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_smoke.626755156 Sep 01 08:24:54 PM UTC 24 Sep 01 08:24:56 PM UTC 24 32095689 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset.3004477470 Sep 01 08:24:56 PM UTC 24 Sep 01 08:24:58 PM UTC 24 62858453 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup_reset.2687900883 Sep 01 08:24:56 PM UTC 24 Sep 01 08:24:58 PM UTC 24 327280159 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup.3067640036 Sep 01 08:24:56 PM UTC 24 Sep 01 08:24:58 PM UTC 24 329240645 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_wakeup_race.520028371 Sep 01 08:24:56 PM UTC 24 Sep 01 08:24:58 PM UTC 24 261572984 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm.3990604243 Sep 01 08:24:54 PM UTC 24 Sep 01 08:24:58 PM UTC 24 807187311 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.1812709919 Sep 01 08:24:57 PM UTC 24 Sep 01 08:24:59 PM UTC 24 37038860 ps
T131 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_aborted_low_power.4139360037 Sep 01 08:24:57 PM UTC 24 Sep 01 08:24:59 PM UTC 24 24464240 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.2325034866 Sep 01 08:24:57 PM UTC 24 Sep 01 08:25:00 PM UTC 24 64745612 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.4194947162 Sep 01 08:24:57 PM UTC 24 Sep 01 08:25:00 PM UTC 24 258262202 ps
T132 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all.3849137421 Sep 01 08:24:54 PM UTC 24 Sep 01 08:25:00 PM UTC 24 1566353925 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_glitch.2057257412 Sep 01 08:24:59 PM UTC 24 Sep 01 08:25:01 PM UTC 24 63146976 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_smoke.319076978 Sep 01 08:25:01 PM UTC 24 Sep 01 08:25:03 PM UTC 24 29755668 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_global_esc.3322178555 Sep 01 08:24:59 PM UTC 24 Sep 01 08:25:01 PM UTC 24 35757134 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3309563675 Sep 01 08:24:57 PM UTC 24 Sep 01 08:25:02 PM UTC 24 1189216730 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_invalid.2322975849 Sep 01 08:25:00 PM UTC 24 Sep 01 08:25:02 PM UTC 24 72103594 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_disable_rom_integrity_check.810726085 Sep 01 08:24:59 PM UTC 24 Sep 01 08:25:02 PM UTC 24 98667704 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_escalation_timeout.4252433290 Sep 01 08:24:59 PM UTC 24 Sep 01 08:25:02 PM UTC 24 111291361 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3044467816 Sep 01 08:24:57 PM UTC 24 Sep 01 08:25:02 PM UTC 24 920442803 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset_invalid.3660023796 Sep 01 08:25:00 PM UTC 24 Sep 01 08:25:02 PM UTC 24 106452820 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm.2273594285 Sep 01 08:25:00 PM UTC 24 Sep 01 08:25:02 PM UTC 24 501241087 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset.1572778701 Sep 01 08:25:01 PM UTC 24 Sep 01 08:25:03 PM UTC 24 26264419 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup.1940713961 Sep 01 08:25:02 PM UTC 24 Sep 01 08:25:05 PM UTC 24 164126044 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup_reset.1640167480 Sep 01 08:25:02 PM UTC 24 Sep 01 08:25:05 PM UTC 24 91187320 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_aborted_low_power.145418285 Sep 01 08:25:02 PM UTC 24 Sep 01 08:25:05 PM UTC 24 57241987 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.195397401 Sep 01 08:25:02 PM UTC 24 Sep 01 08:25:05 PM UTC 24 96816843 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_wakeup_race.3164220536 Sep 01 08:25:02 PM UTC 24 Sep 01 08:25:05 PM UTC 24 228567039 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.1638414470 Sep 01 08:25:04 PM UTC 24 Sep 01 08:25:06 PM UTC 24 38502821 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_global_esc.2572967688 Sep 01 08:25:04 PM UTC 24 Sep 01 08:25:06 PM UTC 24 25710513 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_glitch.2352783709 Sep 01 08:25:04 PM UTC 24 Sep 01 08:25:06 PM UTC 24 84330966 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all_with_rand_reset.157406199 Sep 01 08:25:00 PM UTC 24 Sep 01 08:25:06 PM UTC 24 4912530404 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_disable_rom_integrity_check.2425493063 Sep 01 08:25:04 PM UTC 24 Sep 01 08:25:06 PM UTC 24 78672977 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_escalation_timeout.212938017 Sep 01 08:25:04 PM UTC 24 Sep 01 08:25:06 PM UTC 24 1019685792 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all_with_rand_reset.2459559972 Sep 01 08:24:49 PM UTC 24 Sep 01 08:25:07 PM UTC 24 4347067385 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_ctrl_config_regwen.994887351 Sep 01 08:25:04 PM UTC 24 Sep 01 08:25:07 PM UTC 24 223340906 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_invalid.1277793119 Sep 01 08:25:05 PM UTC 24 Sep 01 08:25:07 PM UTC 24 54634428 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1024180458 Sep 01 08:25:02 PM UTC 24 Sep 01 08:25:07 PM UTC 24 1316673429 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset_invalid.3794829929 Sep 01 08:25:05 PM UTC 24 Sep 01 08:25:07 PM UTC 24 191216400 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.761559232 Sep 01 08:25:02 PM UTC 24 Sep 01 08:25:08 PM UTC 24 1121100740 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset.558773265 Sep 01 08:25:06 PM UTC 24 Sep 01 08:25:08 PM UTC 24 57329337 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_smoke.1032577386 Sep 01 08:25:06 PM UTC 24 Sep 01 08:25:09 PM UTC 24 31973420 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all.2867740473 Sep 01 08:25:06 PM UTC 24 Sep 01 08:25:09 PM UTC 24 90596679 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_wakeup_race.2215337263 Sep 01 08:25:07 PM UTC 24 Sep 01 08:25:09 PM UTC 24 82761923 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup.4208555875 Sep 01 08:25:07 PM UTC 24 Sep 01 08:25:09 PM UTC 24 182302033 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm.2877266829 Sep 01 08:25:06 PM UTC 24 Sep 01 08:25:09 PM UTC 24 607287338 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all.2360794418 Sep 01 08:25:01 PM UTC 24 Sep 01 08:25:09 PM UTC 24 2323432018 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_aborted_low_power.315070671 Sep 01 08:25:08 PM UTC 24 Sep 01 08:25:10 PM UTC 24 33617721 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.416825291 Sep 01 08:25:08 PM UTC 24 Sep 01 08:25:10 PM UTC 24 28658948 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.836229685 Sep 01 08:25:08 PM UTC 24 Sep 01 08:25:11 PM UTC 24 253293187 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.2032476362 Sep 01 08:25:08 PM UTC 24 Sep 01 08:25:11 PM UTC 24 103729993 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup_reset.3796187673 Sep 01 08:25:08 PM UTC 24 Sep 01 08:25:11 PM UTC 24 391819344 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_glitch.277436852 Sep 01 08:25:09 PM UTC 24 Sep 01 08:25:12 PM UTC 24 61598348 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_global_esc.3004226692 Sep 01 08:25:09 PM UTC 24 Sep 01 08:25:12 PM UTC 24 47366885 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_disable_rom_integrity_check.371602592 Sep 01 08:25:10 PM UTC 24 Sep 01 08:25:12 PM UTC 24 94731149 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_invalid.2078236822 Sep 01 08:25:10 PM UTC 24 Sep 01 08:25:12 PM UTC 24 49689707 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_escalation_timeout.3870802475 Sep 01 08:25:09 PM UTC 24 Sep 01 08:25:12 PM UTC 24 379303013 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset_invalid.2414882098 Sep 01 08:25:10 PM UTC 24 Sep 01 08:25:12 PM UTC 24 98602874 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.944327605 Sep 01 08:25:08 PM UTC 24 Sep 01 08:25:13 PM UTC 24 1247540969 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_smoke.354105454 Sep 01 08:25:11 PM UTC 24 Sep 01 08:25:13 PM UTC 24 29021573 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset.1827902665 Sep 01 08:25:11 PM UTC 24 Sep 01 08:25:13 PM UTC 24 121181769 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_wakeup_race.347765679 Sep 01 08:25:11 PM UTC 24 Sep 01 08:25:14 PM UTC 24 344156460 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all_with_rand_reset.2411858801 Sep 01 08:24:54 PM UTC 24 Sep 01 08:25:14 PM UTC 24 4716025820 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1756393149 Sep 01 08:25:08 PM UTC 24 Sep 01 08:25:15 PM UTC 24 823766705 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_aborted_low_power.3549509202 Sep 01 08:25:12 PM UTC 24 Sep 01 08:25:15 PM UTC 24 47834528 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup_reset.1282468930 Sep 01 08:25:12 PM UTC 24 Sep 01 08:25:15 PM UTC 24 110118613 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.301257808 Sep 01 08:25:12 PM UTC 24 Sep 01 08:25:15 PM UTC 24 53455435 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup.3878815143 Sep 01 08:25:12 PM UTC 24 Sep 01 08:25:15 PM UTC 24 332255678 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.2119386660 Sep 01 08:25:14 PM UTC 24 Sep 01 08:25:16 PM UTC 24 42533929 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_global_esc.3498514481 Sep 01 08:25:14 PM UTC 24 Sep 01 08:25:16 PM UTC 24 44479034 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_escalation_timeout.711823315 Sep 01 08:25:14 PM UTC 24 Sep 01 08:25:16 PM UTC 24 560030000 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.940926999 Sep 01 08:25:12 PM UTC 24 Sep 01 08:25:16 PM UTC 24 1016446557 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.86778077 Sep 01 08:25:14 PM UTC 24 Sep 01 08:25:16 PM UTC 24 176074876 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all.194739361 Sep 01 08:25:17 PM UTC 24 Sep 01 08:25:26 PM UTC 24 3432681858 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all.2066831138 Sep 01 08:25:11 PM UTC 24 Sep 01 08:25:17 PM UTC 24 1926036693 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2696942967 Sep 01 08:25:12 PM UTC 24 Sep 01 08:25:17 PM UTC 24 1285258690 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_glitch.1494783797 Sep 01 08:25:15 PM UTC 24 Sep 01 08:25:17 PM UTC 24 49543528 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_invalid.3961992286 Sep 01 08:25:15 PM UTC 24 Sep 01 08:25:17 PM UTC 24 112449335 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_disable_rom_integrity_check.2652940876 Sep 01 08:25:15 PM UTC 24 Sep 01 08:25:17 PM UTC 24 63895211 ps
T227 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset_invalid.2595646680 Sep 01 08:25:15 PM UTC 24 Sep 01 08:25:18 PM UTC 24 99675052 ps
T228 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_wakeup_race.823586089 Sep 01 08:25:17 PM UTC 24 Sep 01 08:25:19 PM UTC 24 68650439 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup.593490288 Sep 01 08:25:23 PM UTC 24 Sep 01 08:25:26 PM UTC 24 174538326 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_smoke.2483281390 Sep 01 08:25:17 PM UTC 24 Sep 01 08:25:19 PM UTC 24 30030755 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup.4064615462 Sep 01 08:25:17 PM UTC 24 Sep 01 08:25:20 PM UTC 24 29870865 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset.711111700 Sep 01 08:25:17 PM UTC 24 Sep 01 08:25:20 PM UTC 24 84212161 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup_reset.3946665729 Sep 01 08:25:17 PM UTC 24 Sep 01 08:25:20 PM UTC 24 385046368 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.2879382215 Sep 01 08:25:18 PM UTC 24 Sep 01 08:25:21 PM UTC 24 32544151 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_aborted_low_power.1691462706 Sep 01 08:25:18 PM UTC 24 Sep 01 08:25:21 PM UTC 24 254591885 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.2998765203 Sep 01 08:25:18 PM UTC 24 Sep 01 08:25:22 PM UTC 24 70082398 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_global_esc.2254552787 Sep 01 08:25:18 PM UTC 24 Sep 01 08:25:22 PM UTC 24 106953166 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_glitch.2842535226 Sep 01 08:25:19 PM UTC 24 Sep 01 08:25:22 PM UTC 24 43734117 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_escalation_timeout.2723881886 Sep 01 08:25:18 PM UTC 24 Sep 01 08:25:22 PM UTC 24 169258282 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.2758150890 Sep 01 08:25:18 PM UTC 24 Sep 01 08:25:23 PM UTC 24 203908983 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all.3833286437 Sep 01 08:25:21 PM UTC 24 Sep 01 08:25:23 PM UTC 24 43614171 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_invalid.3034082143 Sep 01 08:25:21 PM UTC 24 Sep 01 08:25:23 PM UTC 24 59377308 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_disable_rom_integrity_check.1707803940 Sep 01 08:25:21 PM UTC 24 Sep 01 08:25:23 PM UTC 24 63325509 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset_invalid.2399056906 Sep 01 08:25:21 PM UTC 24 Sep 01 08:25:23 PM UTC 24 160978032 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_smoke.276251561 Sep 01 08:25:22 PM UTC 24 Sep 01 08:25:24 PM UTC 24 260920762 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset.4051387057 Sep 01 08:25:22 PM UTC 24 Sep 01 08:25:24 PM UTC 24 67647929 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_wakeup_race.856733036 Sep 01 08:25:22 PM UTC 24 Sep 01 08:25:25 PM UTC 24 144714244 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2369915750 Sep 01 08:25:18 PM UTC 24 Sep 01 08:25:25 PM UTC 24 1249006769 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_aborted_low_power.2036490079 Sep 01 08:25:23 PM UTC 24 Sep 01 08:25:26 PM UTC 24 26328192 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.358549592 Sep 01 08:25:18 PM UTC 24 Sep 01 08:25:26 PM UTC 24 866305108 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup_reset.80726172 Sep 01 08:25:23 PM UTC 24 Sep 01 08:25:26 PM UTC 24 546286960 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.1577581160 Sep 01 08:25:25 PM UTC 24 Sep 01 08:25:27 PM UTC 24 30692634 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_global_esc.3108086525 Sep 01 08:25:25 PM UTC 24 Sep 01 08:25:27 PM UTC 24 32196484 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.706742983 Sep 01 08:25:25 PM UTC 24 Sep 01 08:25:27 PM UTC 24 77565246 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.3957909498 Sep 01 08:25:25 PM UTC 24 Sep 01 08:25:27 PM UTC 24 165232495 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_escalation_timeout.1346470598 Sep 01 08:25:25 PM UTC 24 Sep 01 08:25:28 PM UTC 24 112631707 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2265132932 Sep 01 08:25:23 PM UTC 24 Sep 01 08:25:28 PM UTC 24 1310186196 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_glitch.2820672817 Sep 01 08:25:26 PM UTC 24 Sep 01 08:25:28 PM UTC 24 51770261 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_disable_rom_integrity_check.4006414670 Sep 01 08:25:26 PM UTC 24 Sep 01 08:25:29 PM UTC 24 70196902 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset_invalid.2076483937 Sep 01 08:25:26 PM UTC 24 Sep 01 08:25:29 PM UTC 24 101570067 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_invalid.731680045 Sep 01 08:25:28 PM UTC 24 Sep 01 08:25:30 PM UTC 24 42612718 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3376376545 Sep 01 08:25:25 PM UTC 24 Sep 01 08:25:30 PM UTC 24 974347612 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset.2882392979 Sep 01 08:25:28 PM UTC 24 Sep 01 08:25:30 PM UTC 24 27450409 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_smoke.716372783 Sep 01 08:25:28 PM UTC 24 Sep 01 08:25:30 PM UTC 24 30314481 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup.1450389063 Sep 01 08:25:28 PM UTC 24 Sep 01 08:25:30 PM UTC 24 79369362 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_aborted_low_power.2036421519 Sep 01 08:25:28 PM UTC 24 Sep 01 08:25:30 PM UTC 24 25337251 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_wakeup_race.1820127380 Sep 01 08:25:28 PM UTC 24 Sep 01 08:25:31 PM UTC 24 371658852 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup_reset.2777896967 Sep 01 08:25:28 PM UTC 24 Sep 01 08:25:31 PM UTC 24 304507327 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.3855133263 Sep 01 08:25:29 PM UTC 24 Sep 01 08:25:31 PM UTC 24 65325457 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.2210572453 Sep 01 08:25:29 PM UTC 24 Sep 01 08:25:31 PM UTC 24 39166801 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_smoke.3838807441 Sep 01 08:25:40 PM UTC 24 Sep 01 08:25:42 PM UTC 24 58481900 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all_with_rand_reset.1793581344 Sep 01 08:25:15 PM UTC 24 Sep 01 08:25:33 PM UTC 24 2919422216 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset.1459668091 Sep 01 08:25:40 PM UTC 24 Sep 01 08:25:43 PM UTC 24 63567194 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_global_esc.3035199393 Sep 01 08:25:30 PM UTC 24 Sep 01 08:25:33 PM UTC 24 52431822 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_glitch.315184486 Sep 01 08:25:30 PM UTC 24 Sep 01 08:25:33 PM UTC 24 50330021 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_escalation_timeout.3465327462 Sep 01 08:25:30 PM UTC 24 Sep 01 08:25:33 PM UTC 24 290915446 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all_with_rand_reset.3318991635 Sep 01 08:25:21 PM UTC 24 Sep 01 08:25:33 PM UTC 24 4350118015 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.1117195714 Sep 01 08:25:30 PM UTC 24 Sep 01 08:25:33 PM UTC 24 416906820 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.911985115 Sep 01 08:25:29 PM UTC 24 Sep 01 08:25:34 PM UTC 24 1171098073 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.679925430 Sep 01 08:25:29 PM UTC 24 Sep 01 08:25:34 PM UTC 24 1497581247 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_glitch.1310396762 Sep 01 08:25:43 PM UTC 24 Sep 01 08:25:45 PM UTC 24 49153454 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_disable_rom_integrity_check.2190199376 Sep 01 08:25:32 PM UTC 24 Sep 01 08:25:34 PM UTC 24 80051873 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_invalid.666789350 Sep 01 08:25:32 PM UTC 24 Sep 01 08:25:34 PM UTC 24 64024160 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset.1633078671 Sep 01 08:25:32 PM UTC 24 Sep 01 08:25:34 PM UTC 24 45570913 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset_invalid.4189521796 Sep 01 08:25:32 PM UTC 24 Sep 01 08:25:34 PM UTC 24 156172948 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_smoke.3807071351 Sep 01 08:25:32 PM UTC 24 Sep 01 08:25:34 PM UTC 24 38336183 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all.1629594353 Sep 01 08:25:28 PM UTC 24 Sep 01 08:25:35 PM UTC 24 4221129167 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_wakeup_race.1206807976 Sep 01 08:25:32 PM UTC 24 Sep 01 08:25:35 PM UTC 24 147150735 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all_with_rand_reset.2773063649 Sep 01 08:25:06 PM UTC 24 Sep 01 08:25:36 PM UTC 24 4786105165 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_aborted_low_power.536557842 Sep 01 08:25:34 PM UTC 24 Sep 01 08:25:36 PM UTC 24 41167870 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup.2205834470 Sep 01 08:25:33 PM UTC 24 Sep 01 08:25:36 PM UTC 24 584268038 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all.888662113 Sep 01 08:25:32 PM UTC 24 Sep 01 08:25:36 PM UTC 24 864904312 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup_reset.687296595 Sep 01 08:25:33 PM UTC 24 Sep 01 08:25:36 PM UTC 24 359066781 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all_with_rand_reset.1632242470 Sep 01 08:25:28 PM UTC 24 Sep 01 08:25:37 PM UTC 24 1209800441 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.2532418214 Sep 01 08:25:35 PM UTC 24 Sep 01 08:25:38 PM UTC 24 30853839 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_glitch.3233289936 Sep 01 08:25:35 PM UTC 24 Sep 01 08:25:38 PM UTC 24 36625150 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_global_esc.683656238 Sep 01 08:25:35 PM UTC 24 Sep 01 08:25:38 PM UTC 24 27649584 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all_with_rand_reset.4152654309 Sep 01 08:25:11 PM UTC 24 Sep 01 08:25:38 PM UTC 24 4831719584 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.1098988862 Sep 01 08:25:35 PM UTC 24 Sep 01 08:25:38 PM UTC 24 137041356 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_disable_rom_integrity_check.1794285165 Sep 01 08:25:35 PM UTC 24 Sep 01 08:25:38 PM UTC 24 50668813 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_invalid.804443198 Sep 01 08:25:35 PM UTC 24 Sep 01 08:25:38 PM UTC 24 76462642 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset_invalid.1714173761 Sep 01 08:25:35 PM UTC 24 Sep 01 08:25:38 PM UTC 24 219541193 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_ctrl_config_regwen.3518859861 Sep 01 08:25:35 PM UTC 24 Sep 01 08:25:38 PM UTC 24 248765564 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_escalation_timeout.2508450000 Sep 01 08:25:35 PM UTC 24 Sep 01 08:25:38 PM UTC 24 112507692 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.839302185 Sep 01 08:25:34 PM UTC 24 Sep 01 08:25:39 PM UTC 24 813744776 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_wakeup_race.1799508274 Sep 01 08:25:37 PM UTC 24 Sep 01 08:25:39 PM UTC 24 282155121 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_smoke.3701749962 Sep 01 08:25:37 PM UTC 24 Sep 01 08:25:39 PM UTC 24 26984393 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_aborted_low_power.1290076434 Sep 01 08:25:37 PM UTC 24 Sep 01 08:25:39 PM UTC 24 50070931 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset.1780320328 Sep 01 08:25:37 PM UTC 24 Sep 01 08:25:39 PM UTC 24 119809131 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all_with_rand_reset.1031212406 Sep 01 08:25:32 PM UTC 24 Sep 01 08:25:40 PM UTC 24 4156514563 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup_reset.4031596012 Sep 01 08:25:37 PM UTC 24 Sep 01 08:25:40 PM UTC 24 323785260 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup.1079447111 Sep 01 08:25:37 PM UTC 24 Sep 01 08:25:40 PM UTC 24 215719717 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.2780823083 Sep 01 08:25:38 PM UTC 24 Sep 01 08:25:40 PM UTC 24 29834577 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.2129553847 Sep 01 08:25:38 PM UTC 24 Sep 01 08:25:41 PM UTC 24 98508001 ps
T142 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all_with_rand_reset.3657055352 Sep 01 08:25:35 PM UTC 24 Sep 01 08:25:41 PM UTC 24 1690029592 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1153790230 Sep 01 08:25:34 PM UTC 24 Sep 01 08:25:41 PM UTC 24 777623715 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.2400424730 Sep 01 08:25:38 PM UTC 24 Sep 01 08:25:41 PM UTC 24 103619808 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2463047884 Sep 01 08:25:38 PM UTC 24 Sep 01 08:25:41 PM UTC 24 2954410470 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_global_esc.562886173 Sep 01 08:25:40 PM UTC 24 Sep 01 08:25:42 PM UTC 24 121451578 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_glitch.3595007535 Sep 01 08:25:40 PM UTC 24 Sep 01 08:25:42 PM UTC 24 41890435 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4269270529 Sep 01 08:25:37 PM UTC 24 Sep 01 08:25:42 PM UTC 24 879505694 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup.266474415 Sep 01 08:25:41 PM UTC 24 Sep 01 08:25:45 PM UTC 24 314611442 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_disable_rom_integrity_check.3784493266 Sep 01 08:25:40 PM UTC 24 Sep 01 08:25:42 PM UTC 24 54576758 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_invalid.3045547141 Sep 01 08:25:40 PM UTC 24 Sep 01 08:25:42 PM UTC 24 46411269 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_escalation_timeout.2313605881 Sep 01 08:25:40 PM UTC 24 Sep 01 08:25:42 PM UTC 24 358807903 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset_invalid.3653723453 Sep 01 08:25:40 PM UTC 24 Sep 01 08:25:42 PM UTC 24 117743065 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all.4253942298 Sep 01 08:25:37 PM UTC 24 Sep 01 08:25:43 PM UTC 24 1713888708 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_wakeup_race.4181120 Sep 01 08:25:40 PM UTC 24 Sep 01 08:25:43 PM UTC 24 186158193 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.513818789 Sep 01 08:25:42 PM UTC 24 Sep 01 08:25:44 PM UTC 24 41896718 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_aborted_low_power.4113287583 Sep 01 08:25:41 PM UTC 24 Sep 01 08:25:44 PM UTC 24 152385022 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.121713062 Sep 01 08:25:42 PM UTC 24 Sep 01 08:25:44 PM UTC 24 42356045 ps
T310 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_global_esc.3380355768 Sep 01 08:25:42 PM UTC 24 Sep 01 08:25:44 PM UTC 24 42691074 ps
T311 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.3637934212 Sep 01 08:25:41 PM UTC 24 Sep 01 08:25:44 PM UTC 24 62787022 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_escalation_timeout.2963935707 Sep 01 08:25:42 PM UTC 24 Sep 01 08:25:44 PM UTC 24 391216817 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup_reset.245665911 Sep 01 08:25:41 PM UTC 24 Sep 01 08:25:44 PM UTC 24 360772905 ps
T314 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_wakeup.2696538259 Sep 01 08:25:54 PM UTC 24 Sep 01 08:25:56 PM UTC 24 343681022 ps
T315 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_smoke.1166219392 Sep 01 08:25:43 PM UTC 24 Sep 01 08:25:45 PM UTC 24 31153404 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_lowpower_wakeup_race.26404524 Sep 01 08:25:43 PM UTC 24 Sep 01 08:25:45 PM UTC 24 47886133 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_disable_rom_integrity_check.2281144002 Sep 01 08:25:43 PM UTC 24 Sep 01 08:25:45 PM UTC 24 45594438 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_invalid.4189100425 Sep 01 08:25:43 PM UTC 24 Sep 01 08:25:45 PM UTC 24 38211004 ps
T318 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_reset.3333078862 Sep 01 08:25:43 PM UTC 24 Sep 01 08:25:46 PM UTC 24 118247250 ps
T319 /workspaces/repo/scratch/os_regression_2024_08_31/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset_invalid.4118758714 Sep 01 08:25:43 PM UTC 24 Sep 01 08:25:46 PM UTC 24 101536777 ps