Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	374438	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

145189

1

T1

35

T2

4

T3

25

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	266732	1			T1	57		T2	12		T3	72
values[0x0]	125769	1			T1	7		T2	8		T3	25
values[0x1]	127126	1			T1	3		T2	2		T3	21

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	296641	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

222986

1

T1

43

T2

6

T3

47

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1566	1			T4	1		T5	1		T9	2
valid_sources[0x01]	1667	1			T3	1		T9	10		T34	5
valid_sources[0x02]	1387	1			T9	8		T34	2		T24	7
valid_sources[0x03]	1622	1			T3	2		T4	1		T9	5
valid_sources[0x04]	2820	1			T5	2		T34	4		T24	3
valid_sources[0x05]	7227	1			T4	1		T9	1		T34	6
valid_sources[0x06]	1763	1			T4	2		T9	3		T34	3
valid_sources[0x07]	1749	1			T1	1		T3	1		T4	1
valid_sources[0x08]	1910	1			T1	2		T5	5		T9	5
valid_sources[0x09]	1625	1			T1	1		T9	4		T34	1
valid_sources[0x0a]	1958	1			T3	1		T4	3		T9	7
valid_sources[0x0b]	1373	1			T13	6		T34	3		T24	9
valid_sources[0x0c]	1298	1			T34	4		T24	3		T40	3
valid_sources[0x0d]	1800	1			T9	1		T34	3		T24	3
valid_sources[0x0e]	1588	1			T4	2		T5	2		T34	7
valid_sources[0x0f]	1506	1			T9	10		T34	4		T24	3
valid_sources[0x10]	2006	1			T1	1		T3	1		T4	1
valid_sources[0x11]	1579	1			T1	2		T5	2		T9	14
valid_sources[0x12]	1677	1			T1	1		T9	5		T34	4
valid_sources[0x13]	2440	1			T4	1		T34	2		T24	3
valid_sources[0x14]	1838	1			T3	1		T5	2		T34	5
valid_sources[0x15]	1555	1			T4	1		T5	2		T9	3
valid_sources[0x16]	2175	1			T3	1		T34	4		T24	9
valid_sources[0x17]	1750	1			T5	1		T9	5		T26	4
valid_sources[0x18]	1836	1			T4	2		T9	5		T34	6
valid_sources[0x19]	2679	1			T4	1		T34	8		T24	3
valid_sources[0x1a]	1364	1			T3	1		T9	20		T34	2
valid_sources[0x1b]	1662	1			T4	1		T34	3		T24	13
valid_sources[0x1c]	2492	1			T34	2		T24	5		T14	1
valid_sources[0x1d]	2048	1			T4	2		T5	2		T34	3
valid_sources[0x1e]	4260	1			T3	1		T5	5		T9	4
valid_sources[0x1f]	1692	1			T1	1		T5	1		T9	11
valid_sources[0x20]	1593	1			T34	3		T24	5		T14	1
valid_sources[0x21]	2281	1			T1	1		T3	1		T34	2
valid_sources[0x22]	1636	1			T4	2		T5	4		T34	4
valid_sources[0x23]	1465	1			T1	2		T3	1		T34	5
valid_sources[0x24]	2489	1			T9	3		T34	3		T24	3
valid_sources[0x25]	2490	1			T3	1		T34	8		T24	2
valid_sources[0x26]	1644	1			T5	5		T34	4		T24	6
valid_sources[0x27]	5000	1			T34	2		T24	3		T32	214
valid_sources[0x28]	2874	1			T3	1		T4	1		T8	224
valid_sources[0x29]	1358	1			T5	2		T9	8		T34	4
valid_sources[0x2a]	2202	1			T3	1		T4	1		T7	244
valid_sources[0x2b]	1761	1			T9	7		T34	4		T24	2
valid_sources[0x2c]	2319	1			T1	2		T3	1		T9	6
valid_sources[0x2d]	1794	1			T1	1		T13	2		T36	5
valid_sources[0x2e]	2233	1			T34	4		T24	4		T14	2
valid_sources[0x2f]	2940	1			T5	1		T9	14		T34	3
valid_sources[0x30]	1732	1			T2	22		T4	1		T5	1
valid_sources[0x31]	1569	1			T1	1		T4	1		T9	4
valid_sources[0x32]	3233	1			T9	11		T34	4		T24	5
valid_sources[0x33]	1630	1			T1	1		T9	7		T34	4
valid_sources[0x34]	1920	1			T5	2		T34	5		T24	6
valid_sources[0x35]	1801	1			T4	1		T9	9		T13	4
valid_sources[0x36]	1489	1			T4	2		T9	3		T34	1
valid_sources[0x37]	1551	1			T9	6		T34	4		T24	7
valid_sources[0x38]	1949	1			T24	5		T25	1		T75	1
valid_sources[0x39]	1825	1			T5	1		T9	10		T15	1
valid_sources[0x3a]	3063	1			T9	1		T13	1		T34	6
valid_sources[0x3b]	2865	1			T3	1		T34	3		T24	3
valid_sources[0x3c]	1666	1			T1	1		T9	4		T34	3
valid_sources[0x3d]	1376	1			T1	1		T4	3		T34	3
valid_sources[0x3e]	2721	1			T1	1		T3	2		T9	5
valid_sources[0x3f]	1732	1			T3	1		T4	1		T5	5
valid_sources[0x40]	2319	1			T3	1		T9	5		T34	4
valid_sources[0x41]	1546	1			T3	1		T4	1		T9	7
valid_sources[0x42]	1838	1			T1	1		T5	3		T34	3
valid_sources[0x43]	1518	1			T3	2		T4	1		T5	2
valid_sources[0x44]	1926	1			T3	1		T9	6		T34	5
valid_sources[0x45]	1472	1			T1	1		T9	3		T36	6
valid_sources[0x46]	1516	1			T9	9		T34	5		T24	3
valid_sources[0x47]	2293	1			T4	2		T34	3		T24	1
valid_sources[0x48]	1788	1			T9	4		T34	1		T14	1
valid_sources[0x49]	2255	1			T3	2		T9	17		T34	2
valid_sources[0x4a]	1470	1			T1	2		T3	2		T9	41
valid_sources[0x4b]	1615	1			T1	1		T5	3		T34	4
valid_sources[0x4c]	1645	1			T9	6		T34	3		T24	7
valid_sources[0x4d]	1643	1			T3	1		T36	11		T26	4
valid_sources[0x4e]	4222	1			T4	1		T9	2		T34	8
valid_sources[0x4f]	1709	1			T5	3		T9	8		T26	6
valid_sources[0x50]	2189	1			T1	1		T4	2		T9	24
valid_sources[0x51]	2050	1			T1	1		T9	3		T34	3
valid_sources[0x52]	2740	1			T4	3		T9	3		T34	7
valid_sources[0x53]	1529	1			T1	1		T9	5		T36	6
valid_sources[0x54]	2493	1			T4	1		T5	5		T34	3
valid_sources[0x55]	2224	1			T1	1		T3	1		T36	6
valid_sources[0x56]	1764	1			T3	1		T9	11		T34	6
valid_sources[0x57]	1542	1			T34	1		T24	4		T148	2
valid_sources[0x58]	1794	1			T9	9		T34	5		T24	5
valid_sources[0x59]	2679	1			T5	4		T9	4		T24	4
valid_sources[0x5a]	2658	1			T3	2		T4	2		T9	6
valid_sources[0x5b]	3126	1			T1	1		T9	9		T34	4
valid_sources[0x5c]	1769	1			T3	1		T4	2		T9	4
valid_sources[0x5d]	2643	1			T1	1		T4	1		T9	4
valid_sources[0x5e]	2715	1			T1	1		T4	1		T9	5
valid_sources[0x5f]	1717	1			T5	2		T9	4		T34	1
valid_sources[0x60]	2665	1			T4	2		T5	2		T34	3
valid_sources[0x61]	1996	1			T9	20		T34	3		T24	3
valid_sources[0x62]	2356	1			T1	1		T3	1		T9	6
valid_sources[0x63]	1615	1			T3	1		T9	6		T34	3
valid_sources[0x64]	1988	1			T3	2		T4	1		T9	5
valid_sources[0x65]	1540	1			T4	3		T9	6		T34	4
valid_sources[0x66]	1278	1			T9	2		T34	8		T24	8
valid_sources[0x67]	1599	1			T9	24		T10	1		T34	5
valid_sources[0x68]	1647	1			T3	1		T34	3		T40	1
valid_sources[0x69]	4354	1			T9	1		T34	2		T24	1
valid_sources[0x6a]	1650	1			T3	3		T9	4		T36	5
valid_sources[0x6b]	1612	1			T4	1		T5	2		T9	18
valid_sources[0x6c]	2620	1			T1	1		T4	2		T9	6
valid_sources[0x6d]	1863	1			T4	1		T5	1		T9	3
valid_sources[0x6e]	2134	1			T3	1		T9	12		T34	4
valid_sources[0x6f]	2025	1			T9	12		T34	4		T24	1
valid_sources[0x70]	1472	1			T1	1		T4	1		T34	3
valid_sources[0x71]	1975	1			T5	3		T36	19		T34	5
valid_sources[0x72]	1706	1			T4	1		T9	5		T34	3
valid_sources[0x73]	1408	1			T4	3		T5	1		T9	7
valid_sources[0x74]	1578	1			T1	1		T4	1		T5	2
valid_sources[0x75]	1943	1			T3	2		T9	10		T34	3
valid_sources[0x76]	1763	1			T1	1		T3	1		T9	2
valid_sources[0x77]	1633	1			T4	1		T9	9		T34	4
valid_sources[0x78]	4126	1			T5	2		T9	5		T34	3
valid_sources[0x79]	1733	1			T3	1		T9	14		T34	1
valid_sources[0x7a]	1589	1			T3	2		T9	12		T34	8
valid_sources[0x7b]	2260	1			T3	1		T9	18		T34	4
valid_sources[0x7c]	1629	1			T4	1		T9	3		T36	16
valid_sources[0x7d]	1490	1			T1	1		T34	5		T24	7
valid_sources[0x7e]	2969	1			T34	3		T74	11		T14	1
valid_sources[0x7f]	1886	1			T3	1		T9	17		T24	5
valid_sources[0x80]	1399	1			T34	1		T35	6		T76	137

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

70363

1

T1

32

T2

3

T3

10

values[0x0]

all_enables

biggest_size

48050

1

T1

2

T2

1

T3

11

values[0x1]

all_enables

biggest_size

26776

1

T1

1

T3

4

T4

3