Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	16494045	14007	0	0
intr_enable_rd_A	16494045	26462	0	0
reset_en_rd_A	16494045	2338	0	0
reset_en_regwen_rd_A	16494045	2076	0	0
wake_info_capture_dis_rd_A	16494045	2042	0	0
wakeup_en_rd_A	16494045	2862	0	0
wakeup_en_regwen_rd_A	16494045	2094	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16494045	14007	0	0
T21	145095	13	0	0
T22	189823	11	0	0
T23	0	65	0	0
T48	0	16	0	0
T49	0	19	0	0
T82	6118	0	0	0
T83	2553	0	0	0
T84	2888	0	0	0
T85	5317	0	0	0
T86	7532	0	0	0
T87	1929	0	0	0
T88	2246	0	0	0
T89	2336	0	0	0
T127	0	10	0	0
T128	0	1	0	0
T129	0	1	0	0
T130	0	56	0	0
T131	0	79	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16494045	26462	0	0
T3	3900	32	0	0
T4	10928	24	0	0
T5	1454	0	0	0
T6	608	0	0	0
T7	4723	0	0	0
T8	10893	0	0	0
T9	83407	173	0	0
T10	1420	0	0	0
T13	1466	0	0	0
T14	0	85	0	0
T29	0	69	0	0
T36	5099	0	0	0
T38	0	61	0	0
T59	0	80	0	0
T75	0	13	0	0
T78	0	117	0	0
T132	0	163	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16494045	2338	0	0
T17	3171	0	0	0
T27	30606	0	0	0
T48	60564	5	0	0
T80	0	27	0	0
T81	0	14	0	0
T92	0	12	0	0
T98	50929	0	0	0
T127	191059	29	0	0
T128	0	22	0	0
T129	0	9	0	0
T133	0	11	0	0
T134	0	23	0	0
T135	0	12	0	0
T136	3094	0	0	0
T137	2446	0	0	0
T138	9463	0	0	0
T139	8319	0	0	0
T140	1965	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16494045	2076	0	0
T17	3171	0	0	0
T27	30606	0	0	0
T48	60564	5	0	0
T80	0	7	0	0
T81	0	17	0	0
T92	0	10	0	0
T98	50929	0	0	0
T127	191059	3	0	0
T128	0	4	0	0
T129	0	13	0	0
T133	0	5	0	0
T134	0	13	0	0
T135	0	6	0	0
T136	3094	0	0	0
T137	2446	0	0	0
T138	9463	0	0	0
T139	8319	0	0	0
T140	1965	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16494045	2042	0	0
T17	3171	0	0	0
T27	30606	0	0	0
T48	60564	8	0	0
T80	0	17	0	0
T81	0	15	0	0
T92	0	15	0	0
T98	50929	0	0	0
T127	191059	2	0	0
T128	0	22	0	0
T129	0	1	0	0
T133	0	6	0	0
T134	0	7	0	0
T135	0	4	0	0
T136	3094	0	0	0
T137	2446	0	0	0
T138	9463	0	0	0
T139	8319	0	0	0
T140	1965	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16494045	2862	0	0
T17	3171	0	0	0
T27	30606	0	0	0
T48	60564	9	0	0
T80	0	20	0	0
T81	0	12	0	0
T92	0	4	0	0
T98	50929	0	0	0
T127	191059	4	0	0
T128	0	14	0	0
T129	0	2	0	0
T133	0	8	0	0
T134	0	14	0	0
T135	0	10	0	0
T136	3094	0	0	0
T137	2446	0	0	0
T138	9463	0	0	0
T139	8319	0	0	0
T140	1965	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16494045	2094	0	0
T17	3171	0	0	0
T27	30606	0	0	0
T48	60564	1	0	0
T80	0	10	0	0
T81	0	16	0	0
T92	0	18	0	0
T98	50929	0	0	0
T127	191059	15	0	0
T128	0	16	0	0
T129	0	11	0	0
T133	0	3	0	0
T134	0	7	0	0
T135	0	11	0	0
T136	3094	0	0	0
T137	2446	0	0	0
T138	9463	0	0	0
T139	8319	0	0	0
T140	1965	0	0	0