Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	47857209	106615	0	0
StatusRise_A	47857209	119739	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47857209	106615	0	0
T1	6690	6	0	0
T2	6651	3	0	0
T3	11700	45	0	0
T4	32784	27	0	0
T5	4362	27	0	0
T6	1824	3	0	0
T7	14169	3	0	0
T8	32679	45	0	0
T9	250221	285	0	0
T10	4260	0	0	0
T13	0	15	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47857209	119739	0	0
T1	6690	9	0	0
T2	6651	6	0	0
T3	11700	48	0	0
T4	32784	30	0	0
T5	4362	29	0	0
T6	1824	9	0	0
T7	14169	6	0	0
T8	32679	48	0	0
T9	250221	321	0	0
T10	4260	15	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	15952403	39631	0	0
StatusRise_A	15952403	44332	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15952403	39631	0	0
T1	2230	2	0	0
T2	2217	1	0	0
T3	3900	15	0	0
T4	10928	11	0	0
T5	1454	9	0	0
T6	608	1	0	0
T7	4723	1	0	0
T8	10893	17	0	0
T9	83407	108	0	0
T10	1420	0	0	0
T13	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15952403	44332	0	0
T1	2230	3	0	0
T2	2217	2	0	0
T3	3900	16	0	0
T4	10928	12	0	0
T5	1454	10	0	0
T6	608	3	0	0
T7	4723	2	0	0
T8	10893	18	0	0
T9	83407	122	0	0
T10	1420	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	15952403	39632	0	0
StatusRise_A	15952403	44334	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15952403	39632	0	0
T1	2230	2	0	0
T2	2217	1	0	0
T3	3900	15	0	0
T4	10928	11	0	0
T5	1454	9	0	0
T6	608	1	0	0
T7	4723	1	0	0
T8	10893	17	0	0
T9	83407	108	0	0
T10	1420	0	0	0
T13	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15952403	44334	0	0
T1	2230	3	0	0
T2	2217	2	0	0
T3	3900	16	0	0
T4	10928	12	0	0
T5	1454	10	0	0
T6	608	3	0	0
T7	4723	2	0	0
T8	10893	18	0	0
T9	83407	122	0	0
T10	1420	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	15952403	27352	0	0
StatusRise_A	15952403	31073	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15952403	27352	0	0
T1	2230	2	0	0
T2	2217	1	0	0
T3	3900	15	0	0
T4	10928	5	0	0
T5	1454	9	0	0
T6	608	1	0	0
T7	4723	1	0	0
T8	10893	11	0	0
T9	83407	69	0	0
T10	1420	0	0	0
T13	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15952403	31073	0	0
T1	2230	3	0	0
T2	2217	2	0	0
T3	3900	16	0	0
T4	10928	6	0	0
T5	1454	9	0	0
T6	608	3	0	0
T7	4723	2	0	0
T8	10893	12	0	0
T9	83407	77	0	0
T10	1420	5	0	0