Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

41                      
42         1/1            always_comb reset_or_disable = !rst_ni || disable_sva;
           Tests:       T1 T2 T3 
43         1/1            always_comb esc_reset_or_disable = !rst_esc_ni || disable_sva;
           Tests:       T1 T2 T3 
44         1/1            always_comb slow_reset_or_disable = !rst_slow_ni || disable_sva;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	15952983	8842	0	0
EscTimeoutStoppedByClReset_A	15952403	2143880	0	0
EscTimeoutTriggersReset_A	4139249	435	0	0
RomAllowActiveState_A	15952403	43897	0	0
RomAllowCheckGoodState_A	15952403	43948	0	0
RomBlockActiveState_A	15952403	27612	0	0
RomBlockCheckGoodState_A	15952403	363332	0	0
RomIntgChkDisFalse_A	15952403	15419851	0	0
RomIntgChkDisTrue_A	15952403	118622	0	0
RstreqChkEsctimeout_A	15952403	3383	0	0
RstreqChkFsmterm_A	15952403	160	0	0
RstreqChkGlbesc_A	15952403	3383	0	0
RstreqChkMainpd_A	15952403	674892	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15952983	8842	0	0
T11	10373	327	0	0
T14	3268	0	0	0
T18	12715	0	0	0
T24	52199	0	0	0
T29	16756	0	0	0
T31	0	89	0	0
T37	1622	0	0	0
T72	1109	0	0	0
T74	3340	0	0	0
T138	0	104	0	0
T141	0	45	0	0
T142	0	84	0	0
T143	0	144	0	0
T144	0	388	0	0
T145	0	86	0	0
T146	0	320	0	0
T147	0	3	0	0
T148	1617	0	0	0
T149	3532	0	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15952403	2143880	0	0
T1	2230	13	0	0
T2	2217	0	0	0
T3	3900	422	0	0
T4	10928	2853	0	0
T5	1454	15	0	0
T6	608	12	0	0
T7	4723	16	0	0
T8	10893	1487	0	0
T9	83407	12116	0	0
T10	1420	36	0	0
T13	0	86	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4139249	435	0	0
T6	388	6	0	0
T7	366	0	0	0
T8	1143	0	0	0
T9	7988	0	0	0
T10	793	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T13	508	0	0	0
T15	367	0	0	0
T26	1234	0	0	0
T31	0	5	0	0
T36	2038	0	0	0
T39	355	0	0	0
T87	0	2	0	0
T138	0	6	0	0
T141	0	5	0	0
T142	0	6	0	0
T150	0	4	0	0
T151	0	2	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15952403	43897	0	0
T1	2230	3	0	0
T2	2217	2	0	0
T3	3900	16	0	0
T4	10928	12	0	0
T5	1454	10	0	0
T6	608	3	0	0
T7	4723	2	0	0
T8	10893	18	0	0
T9	83407	122	0	0
T10	1420	5	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15952403	43948	0	0
T1	2230	3	0	0
T2	2217	2	0	0
T3	3900	16	0	0
T4	10928	12	0	0
T5	1454	10	0	0
T6	608	3	0	0
T7	4723	2	0	0
T8	10893	18	0	0
T9	83407	122	0	0
T10	1420	5	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15952403	27612	0	0
T11	10372	0	0	0
T13	1466	247	0	0
T15	3714	0	0	0
T24	52198	0	0	0
T25	0	587	0	0
T26	3389	0	0	0
T34	18117	14	0	0
T36	5099	0	0	0
T37	1621	0	0	0
T39	1862	0	0	0
T132	0	8	0	0
T137	0	509	0	0
T148	1616	0	0	0
T152	0	164	0	0
T153	0	3	0	0
T154	0	1029	0	0
T155	0	216	0	0
T156	0	53	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15952403	363332	0	0
T8	10893	230	0	0
T9	83407	506	0	0
T10	1420	0	0	0
T11	10372	0	0	0
T13	1466	87	0	0
T15	3714	0	0	0
T24	0	4132	0	0
T25	0	354	0	0
T26	3389	0	0	0
T34	18117	1285	0	0
T35	0	3550	0	0
T36	5099	0	0	0
T39	1862	0	0	0
T77	0	435	0	0
T148	0	45	0	0
T157	0	299	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15952403	15419851	0	0
T1	2230	2132	0	0
T2	2217	2137	0	0
T3	3900	3832	0	0
T4	10928	10848	0	0
T5	1454	1378	0	0
T6	608	464	0	0
T7	4723	4669	0	0
T8	10893	10821	0	0
T9	83407	82291	0	0
T10	1420	1102	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15952403	118622	0	0
T11	10372	0	0	0
T13	1466	34	0	0
T15	3714	0	0	0
T24	52198	4487	0	0
T25	0	51	0	0
T26	3389	0	0	0
T34	18117	0	0	0
T36	5099	0	0	0
T37	1621	0	0	0
T39	1862	0	0	0
T78	0	2253	0	0
T132	0	212	0	0
T137	0	98	0	0
T148	1616	0	0	0
T152	0	161	0	0
T158	0	11412	0	0
T159	0	426	0	0
T160	0	3284	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15952403	3383	0	0
T3	3900	8	0	0
T4	10928	0	0	0
T5	1454	0	0	0
T6	608	1	0	0
T7	4723	0	0	0
T8	10893	0	0	0
T9	83407	0	0	0
T10	1420	4	0	0
T11	0	2	0	0
T12	0	1	0	0
T13	1466	5	0	0
T18	0	10	0	0
T26	0	3	0	0
T30	0	5	0	0
T36	5099	0	0	0
T37	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15952403	160	0	0
T12	1258	0	0	0
T14	3267	0	0	0
T16	4041	0	0	0
T18	12714	20	0	0
T19	0	20	0	0
T20	0	40	0	0
T25	2787	0	0	0
T27	0	40	0	0
T28	0	40	0	0
T29	16755	0	0	0
T30	2064	0	0	0
T31	9540	0	0	0
T32	4289	0	0	0
T33	3229	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15952403	3383	0	0
T3	3900	8	0	0
T4	10928	0	0	0
T5	1454	0	0	0
T6	608	1	0	0
T7	4723	0	0	0
T8	10893	0	0	0
T9	83407	0	0	0
T10	1420	4	0	0
T11	0	2	0	0
T12	0	1	0	0
T13	1466	5	0	0
T18	0	10	0	0
T26	0	3	0	0
T30	0	5	0	0
T36	5099	0	0	0
T37	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15952403	674892	0	0
T3	3900	392	0	0
T4	10928	0	0	0
T5	1454	0	0	0
T6	608	0	0	0
T7	4723	0	0	0
T8	10893	1289	0	0
T9	83407	2742	0	0
T10	1420	0	0	0
T13	1466	21	0	0
T15	0	28	0	0
T16	0	23	0	0
T24	0	5385	0	0
T25	0	83	0	0
T26	0	127	0	0
T34	0	1544	0	0
T36	5099	0	0	0