Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5336 |
1 |
|
|
T3 |
10 |
|
T4 |
9 |
|
T40 |
8 |
auto[1] |
15344 |
1 |
|
|
T1 |
1 |
|
T3 |
5 |
|
T4 |
7 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9333 |
1 |
|
|
T3 |
8 |
|
T4 |
9 |
|
T5 |
8 |
auto[1] |
11347 |
1 |
|
|
T1 |
1 |
|
T3 |
7 |
|
T4 |
7 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9773 |
1 |
|
|
T3 |
7 |
|
T4 |
8 |
|
T5 |
9 |
auto[1] |
10907 |
1 |
|
|
T1 |
1 |
|
T3 |
8 |
|
T4 |
8 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1184 |
1 |
|
|
T3 |
3 |
|
T4 |
4 |
|
T40 |
3 |
auto[0] |
auto[0] |
auto[1] |
1250 |
1 |
|
|
T3 |
2 |
|
T4 |
2 |
|
T40 |
5 |
auto[0] |
auto[1] |
auto[0] |
3590 |
1 |
|
|
T3 |
2 |
|
T4 |
2 |
|
T5 |
3 |
auto[0] |
auto[1] |
auto[1] |
3309 |
1 |
|
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
5 |
auto[1] |
auto[0] |
auto[0] |
1227 |
1 |
|
|
T4 |
1 |
|
T34 |
2 |
|
T64 |
4 |
auto[1] |
auto[0] |
auto[1] |
1675 |
1 |
|
|
T3 |
5 |
|
T4 |
2 |
|
T34 |
3 |
auto[1] |
auto[1] |
auto[0] |
3772 |
1 |
|
|
T3 |
2 |
|
T4 |
1 |
|
T5 |
6 |
auto[1] |
auto[1] |
auto[1] |
4673 |
1 |
|
|
T1 |
1 |
|
T4 |
3 |
|
T5 |
4 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5336 |
1 |
|
|
T3 |
10 |
|
T4 |
9 |
|
T40 |
8 |
auto[1] |
15344 |
1 |
|
|
T1 |
1 |
|
T3 |
5 |
|
T4 |
7 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9165 |
1 |
|
|
T3 |
6 |
|
T4 |
8 |
|
T5 |
8 |
auto[1] |
11515 |
1 |
|
|
T1 |
1 |
|
T3 |
9 |
|
T4 |
8 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9864 |
1 |
|
|
T1 |
1 |
|
T3 |
6 |
|
T4 |
9 |
auto[1] |
10816 |
1 |
|
|
T3 |
9 |
|
T4 |
7 |
|
T5 |
11 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1170 |
1 |
|
|
T3 |
1 |
|
T4 |
4 |
|
T40 |
4 |
auto[0] |
auto[0] |
auto[1] |
1275 |
1 |
|
|
T3 |
3 |
|
T4 |
3 |
|
T40 |
1 |
auto[0] |
auto[1] |
auto[0] |
3533 |
1 |
|
|
T3 |
2 |
|
T5 |
3 |
|
T14 |
13 |
auto[0] |
auto[1] |
auto[1] |
3187 |
1 |
|
|
T4 |
1 |
|
T5 |
5 |
|
T40 |
3 |
auto[1] |
auto[0] |
auto[0] |
1238 |
1 |
|
|
T3 |
3 |
|
T4 |
2 |
|
T40 |
1 |
auto[1] |
auto[0] |
auto[1] |
1653 |
1 |
|
|
T3 |
3 |
|
T40 |
2 |
|
T34 |
4 |
auto[1] |
auto[1] |
auto[0] |
3923 |
1 |
|
|
T1 |
1 |
|
T4 |
3 |
|
T5 |
4 |
auto[1] |
auto[1] |
auto[1] |
4701 |
1 |
|
|
T3 |
3 |
|
T4 |
3 |
|
T5 |
6 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5336 |
1 |
|
|
T3 |
10 |
|
T4 |
9 |
|
T40 |
8 |
auto[1] |
15344 |
1 |
|
|
T1 |
1 |
|
T3 |
5 |
|
T4 |
7 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9357 |
1 |
|
|
T3 |
5 |
|
T4 |
5 |
|
T5 |
9 |
auto[1] |
11323 |
1 |
|
|
T1 |
1 |
|
T3 |
10 |
|
T4 |
11 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9705 |
1 |
|
|
T3 |
7 |
|
T4 |
2 |
|
T5 |
9 |
auto[1] |
10975 |
1 |
|
|
T1 |
1 |
|
T3 |
8 |
|
T4 |
14 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1221 |
1 |
|
|
T40 |
2 |
|
T34 |
1 |
|
T36 |
2 |
auto[0] |
auto[0] |
auto[1] |
1265 |
1 |
|
|
T3 |
1 |
|
T4 |
3 |
|
T34 |
1 |
auto[0] |
auto[1] |
auto[0] |
3524 |
1 |
|
|
T3 |
3 |
|
T5 |
4 |
|
T40 |
1 |
auto[0] |
auto[1] |
auto[1] |
3347 |
1 |
|
|
T3 |
1 |
|
T4 |
2 |
|
T5 |
5 |
auto[1] |
auto[0] |
auto[0] |
1176 |
1 |
|
|
T3 |
4 |
|
T4 |
2 |
|
T40 |
3 |
auto[1] |
auto[0] |
auto[1] |
1674 |
1 |
|
|
T3 |
5 |
|
T4 |
4 |
|
T40 |
3 |
auto[1] |
auto[1] |
auto[0] |
3784 |
1 |
|
|
T5 |
5 |
|
T40 |
1 |
|
T14 |
9 |
auto[1] |
auto[1] |
auto[1] |
4689 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
5 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5336 |
1 |
|
|
T3 |
10 |
|
T4 |
9 |
|
T40 |
8 |
auto[1] |
15344 |
1 |
|
|
T1 |
1 |
|
T3 |
5 |
|
T4 |
7 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9410 |
1 |
|
|
T3 |
8 |
|
T4 |
6 |
|
T5 |
8 |
auto[1] |
11270 |
1 |
|
|
T1 |
1 |
|
T3 |
7 |
|
T4 |
10 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9867 |
1 |
|
|
T1 |
1 |
|
T3 |
7 |
|
T4 |
9 |
auto[1] |
10813 |
1 |
|
|
T3 |
8 |
|
T4 |
7 |
|
T5 |
6 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1228 |
1 |
|
|
T3 |
3 |
|
T4 |
4 |
|
T40 |
2 |
auto[0] |
auto[0] |
auto[1] |
1252 |
1 |
|
|
T3 |
2 |
|
T40 |
2 |
|
T64 |
1 |
auto[0] |
auto[1] |
auto[0] |
3612 |
1 |
|
|
T3 |
2 |
|
T4 |
2 |
|
T5 |
4 |
auto[0] |
auto[1] |
auto[1] |
3318 |
1 |
|
|
T3 |
1 |
|
T5 |
4 |
|
T40 |
2 |
auto[1] |
auto[0] |
auto[0] |
1279 |
1 |
|
|
T3 |
1 |
|
T4 |
2 |
|
T40 |
2 |
auto[1] |
auto[0] |
auto[1] |
1577 |
1 |
|
|
T3 |
4 |
|
T4 |
3 |
|
T40 |
2 |
auto[1] |
auto[1] |
auto[0] |
3748 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
auto[1] |
auto[1] |
auto[1] |
4666 |
1 |
|
|
T3 |
1 |
|
T4 |
4 |
|
T5 |
2 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5336 |
1 |
|
|
T3 |
10 |
|
T4 |
9 |
|
T40 |
8 |
auto[1] |
15344 |
1 |
|
|
T1 |
1 |
|
T3 |
5 |
|
T4 |
7 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9458 |
1 |
|
|
T3 |
9 |
|
T4 |
7 |
|
T5 |
5 |
auto[1] |
11222 |
1 |
|
|
T1 |
1 |
|
T3 |
6 |
|
T4 |
9 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9718 |
1 |
|
|
T3 |
3 |
|
T4 |
8 |
|
T5 |
5 |
auto[1] |
10962 |
1 |
|
|
T1 |
1 |
|
T3 |
12 |
|
T4 |
8 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1186 |
1 |
|
|
T4 |
3 |
|
T40 |
3 |
|
T34 |
3 |
auto[0] |
auto[0] |
auto[1] |
1256 |
1 |
|
|
T3 |
5 |
|
T34 |
1 |
|
T36 |
3 |
auto[0] |
auto[1] |
auto[0] |
3646 |
1 |
|
|
T3 |
1 |
|
T5 |
1 |
|
T40 |
1 |
auto[0] |
auto[1] |
auto[1] |
3370 |
1 |
|
|
T3 |
3 |
|
T4 |
4 |
|
T5 |
4 |
auto[1] |
auto[0] |
auto[0] |
1193 |
1 |
|
|
T3 |
2 |
|
T4 |
4 |
|
T40 |
3 |
auto[1] |
auto[0] |
auto[1] |
1701 |
1 |
|
|
T3 |
3 |
|
T4 |
2 |
|
T40 |
2 |
auto[1] |
auto[1] |
auto[0] |
3693 |
1 |
|
|
T4 |
1 |
|
T5 |
4 |
|
T40 |
2 |
auto[1] |
auto[1] |
auto[1] |
4635 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
2 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5336 |
1 |
|
|
T3 |
10 |
|
T4 |
9 |
|
T40 |
8 |
auto[1] |
15344 |
1 |
|
|
T1 |
1 |
|
T3 |
5 |
|
T4 |
7 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9302 |
1 |
|
|
T3 |
8 |
|
T4 |
10 |
|
T5 |
12 |
auto[1] |
11378 |
1 |
|
|
T1 |
1 |
|
T3 |
7 |
|
T4 |
6 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9776 |
1 |
|
|
T1 |
1 |
|
T3 |
3 |
|
T4 |
7 |
auto[1] |
10904 |
1 |
|
|
T3 |
12 |
|
T4 |
9 |
|
T5 |
8 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1222 |
1 |
|
|
T3 |
2 |
|
T4 |
2 |
|
T40 |
2 |
auto[0] |
auto[0] |
auto[1] |
1192 |
1 |
|
|
T3 |
3 |
|
T4 |
5 |
|
T40 |
2 |
auto[0] |
auto[1] |
auto[0] |
3615 |
1 |
|
|
T3 |
1 |
|
T4 |
2 |
|
T5 |
9 |
auto[0] |
auto[1] |
auto[1] |
3273 |
1 |
|
|
T3 |
2 |
|
T4 |
1 |
|
T5 |
3 |
auto[1] |
auto[0] |
auto[0] |
1227 |
1 |
|
|
T4 |
1 |
|
T40 |
2 |
|
T34 |
3 |
auto[1] |
auto[0] |
auto[1] |
1695 |
1 |
|
|
T3 |
5 |
|
T4 |
1 |
|
T40 |
2 |
auto[1] |
auto[1] |
auto[0] |
3712 |
1 |
|
|
T1 |
1 |
|
T4 |
2 |
|
T5 |
1 |
auto[1] |
auto[1] |
auto[1] |
4744 |
1 |
|
|
T3 |
2 |
|
T4 |
2 |
|
T5 |
5 |