Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	397143	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

155141

1

T1

13

T2

14

T3

48

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	289354	1			T1	23		T2	42		T3	91
values[0x0]	131346	1			T1	6		T2	16		T3	61
values[0x1]	131584	1			T1	4		T2	10		T3	49

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	314567	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

237717

1

T1

18

T2

32

T3

80

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1746	1			T2	4		T4	2		T14	1
valid_sources[0x01]	1749	1			T4	1		T5	2		T10	2
valid_sources[0x02]	2412	1			T4	2		T5	3		T14	1
valid_sources[0x03]	1593	1			T3	5		T5	2		T14	5
valid_sources[0x04]	1613	1			T5	1		T10	2		T15	1
valid_sources[0x05]	1679	1			T2	1		T4	1		T10	2
valid_sources[0x06]	1914	1			T2	4		T4	1		T5	3
valid_sources[0x07]	1780	1			T5	1		T10	2		T14	6
valid_sources[0x08]	2302	1			T3	2		T4	2		T5	1
valid_sources[0x09]	1711	1			T3	2		T4	1		T5	6
valid_sources[0x0a]	1888	1			T3	2		T6	1		T10	2
valid_sources[0x0b]	1488	1			T4	1		T34	3		T39	1
valid_sources[0x0c]	1893	1			T4	2		T14	2		T15	9
valid_sources[0x0d]	2132	1			T10	1		T14	2		T15	8
valid_sources[0x0e]	1863	1			T4	1		T5	3		T10	4
valid_sources[0x0f]	1667	1			T5	3		T14	3		T15	3
valid_sources[0x10]	1944	1			T5	2		T14	4		T15	6
valid_sources[0x11]	1972	1			T4	2		T5	2		T15	4
valid_sources[0x12]	1507	1			T4	2		T5	3		T10	1
valid_sources[0x13]	1668	1			T5	1		T15	5		T45	1
valid_sources[0x14]	2132	1			T4	5		T10	1		T14	11
valid_sources[0x15]	1607	1			T2	1		T3	1		T5	1
valid_sources[0x16]	1620	1			T2	2		T5	1		T10	3
valid_sources[0x17]	1564	1			T4	1		T5	2		T14	4
valid_sources[0x18]	2600	1			T2	4		T3	3		T4	1
valid_sources[0x19]	4241	1			T3	3		T10	2		T14	8
valid_sources[0x1a]	2971	1			T4	1		T5	2		T10	1
valid_sources[0x1b]	2052	1			T4	1		T10	1		T15	1
valid_sources[0x1c]	1886	1			T3	2		T10	2		T14	3
valid_sources[0x1d]	1594	1			T4	1		T5	1		T15	1
valid_sources[0x1e]	1548	1			T3	5		T5	2		T14	1
valid_sources[0x1f]	1697	1			T14	3		T15	2		T33	4
valid_sources[0x20]	2355	1			T10	2		T14	9		T15	2
valid_sources[0x21]	3048	1			T3	2		T5	4		T10	8
valid_sources[0x22]	1570	1			T4	3		T10	1		T14	6
valid_sources[0x23]	1711	1			T3	1		T4	1		T5	2
valid_sources[0x24]	2062	1			T15	5		T32	1		T34	1
valid_sources[0x25]	1796	1			T3	2		T14	1		T15	1
valid_sources[0x26]	7483	1			T5	1		T14	8		T15	6
valid_sources[0x27]	2027	1			T4	1		T5	1		T15	4
valid_sources[0x28]	2039	1			T2	2		T4	2		T5	2
valid_sources[0x29]	1845	1			T2	1		T4	1		T5	1
valid_sources[0x2a]	4802	1			T3	2		T5	1		T33	1
valid_sources[0x2b]	1632	1			T4	1		T5	1		T14	5
valid_sources[0x2c]	2283	1			T4	1		T5	3		T33	1
valid_sources[0x2d]	2332	1			T14	12		T15	4		T45	1
valid_sources[0x2e]	1643	1			T4	1		T14	4		T15	4
valid_sources[0x2f]	1658	1			T2	1		T4	2		T5	1
valid_sources[0x30]	1722	1			T10	2		T14	7		T15	16
valid_sources[0x31]	1668	1			T3	2		T5	3		T14	15
valid_sources[0x32]	2324	1			T5	1		T6	1		T14	2
valid_sources[0x33]	1587	1			T2	2		T4	1		T5	1
valid_sources[0x34]	2015	1			T4	1		T5	2		T10	1
valid_sources[0x35]	1572	1			T5	1		T10	3		T14	2
valid_sources[0x36]	2002	1			T4	1		T5	1		T10	3
valid_sources[0x37]	1906	1			T5	2		T6	1		T10	1
valid_sources[0x38]	2013	1			T3	1		T4	1		T5	1
valid_sources[0x39]	2582	1			T10	4		T14	4		T15	1
valid_sources[0x3a]	1746	1			T2	2		T4	2		T5	1
valid_sources[0x3b]	1675	1			T3	3		T4	1		T5	1
valid_sources[0x3c]	2602	1			T10	1		T15	3		T31	1
valid_sources[0x3d]	2472	1			T2	1		T5	4		T14	3
valid_sources[0x3e]	1863	1			T3	1		T5	2		T10	2
valid_sources[0x3f]	1908	1			T10	1		T15	1		T32	1
valid_sources[0x40]	1807	1			T4	1		T6	1		T10	1
valid_sources[0x41]	1772	1			T4	1		T5	4		T14	3
valid_sources[0x42]	1655	1			T10	5		T14	2		T15	10
valid_sources[0x43]	1735	1			T4	1		T5	1		T10	1
valid_sources[0x44]	1554	1			T4	1		T6	1		T15	2
valid_sources[0x45]	1770	1			T3	4		T4	1		T5	1
valid_sources[0x46]	2726	1			T4	2		T5	2		T32	1
valid_sources[0x47]	2803	1			T5	1		T10	1		T15	1
valid_sources[0x48]	1628	1			T2	2		T4	1		T14	5
valid_sources[0x49]	1798	1			T3	4		T4	1		T5	1
valid_sources[0x4a]	3007	1			T5	1		T10	1		T15	13
valid_sources[0x4b]	3125	1			T3	4		T4	1		T5	2
valid_sources[0x4c]	1747	1			T3	1		T83	2		T200	1
valid_sources[0x4d]	2430	1			T10	1		T14	3		T15	7
valid_sources[0x4e]	1543	1			T3	1		T4	1		T10	5
valid_sources[0x4f]	2509	1			T4	1		T10	1		T15	4
valid_sources[0x50]	1746	1			T5	5		T10	2		T14	7
valid_sources[0x51]	1719	1			T4	2		T10	1		T15	14
valid_sources[0x52]	1644	1			T4	2		T5	1		T14	3
valid_sources[0x53]	2910	1			T3	1		T6	1		T14	6
valid_sources[0x54]	2221	1			T3	1		T4	1		T10	3
valid_sources[0x55]	1521	1			T3	2		T5	1		T15	1
valid_sources[0x56]	2347	1			T4	1		T10	1		T14	5
valid_sources[0x57]	1631	1			T5	2		T15	3		T33	1
valid_sources[0x58]	1712	1			T4	3		T14	2		T15	3
valid_sources[0x59]	1570	1			T3	3		T5	1		T14	1
valid_sources[0x5a]	1817	1			T3	2		T4	3		T5	1
valid_sources[0x5b]	2483	1			T4	2		T5	1		T33	3
valid_sources[0x5c]	1690	1			T4	3		T14	6		T15	2
valid_sources[0x5d]	1847	1			T3	7		T5	5		T14	3
valid_sources[0x5e]	2193	1			T3	2		T4	1		T5	3
valid_sources[0x5f]	1566	1			T4	2		T5	3		T14	6
valid_sources[0x60]	2077	1			T3	2		T14	2		T15	1
valid_sources[0x61]	4425	1			T4	1		T5	2		T20	2
valid_sources[0x62]	2031	1			T4	1		T6	1		T15	8
valid_sources[0x63]	2010	1			T5	1		T14	1		T15	4
valid_sources[0x64]	2934	1			T5	3		T10	1		T14	7
valid_sources[0x65]	2767	1			T5	1		T8	1		T10	2
valid_sources[0x66]	1910	1			T4	1		T5	2		T14	18
valid_sources[0x67]	2774	1			T5	1		T10	1		T15	1
valid_sources[0x68]	1448	1			T4	4		T10	1		T14	2
valid_sources[0x69]	1565	1			T5	3		T14	19		T15	1
valid_sources[0x6a]	1587	1			T4	1		T10	2		T15	2
valid_sources[0x6b]	1889	1			T3	5		T4	2		T6	1
valid_sources[0x6c]	2019	1			T3	3		T5	2		T39	1
valid_sources[0x6d]	1896	1			T4	2		T5	1		T14	2
valid_sources[0x6e]	2627	1			T4	6		T10	3		T15	3
valid_sources[0x6f]	2694	1			T10	2		T15	3		T33	2
valid_sources[0x70]	1799	1			T10	1		T15	1		T45	1
valid_sources[0x71]	1808	1			T2	1		T3	3		T4	1
valid_sources[0x72]	1653	1			T3	3		T4	1		T5	3
valid_sources[0x73]	4877	1			T3	1		T4	3		T5	1
valid_sources[0x74]	2266	1			T4	1		T5	3		T6	1
valid_sources[0x75]	9506	1			T4	2		T5	4		T33	3
valid_sources[0x76]	1655	1			T5	1		T10	4		T14	2
valid_sources[0x77]	1860	1			T2	8		T4	3		T6	1
valid_sources[0x78]	2864	1			T4	3		T5	2		T10	2
valid_sources[0x79]	1876	1			T10	1		T14	2		T32	1
valid_sources[0x7a]	1636	1			T4	1		T15	5		T45	1
valid_sources[0x7b]	1821	1			T2	2		T4	1		T5	1
valid_sources[0x7c]	4978	1			T3	1		T4	1		T10	2
valid_sources[0x7d]	2008	1			T1	33		T3	1		T4	1
valid_sources[0x7e]	1498	1			T3	1		T14	4		T15	2
valid_sources[0x7f]	2759	1			T4	2		T5	1		T14	6
valid_sources[0x80]	1991	1			T4	1		T5	3		T10	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

78414

1

T1

10

T2

6

T3

14

values[0x0]

all_enables

biggest_size

49616

1

T1

3

T2

5

T3

28

values[0x1]

all_enables

biggest_size

27111

1

T2

3

T3

6

T4

7