Unified Coverage Report :: Module :: pwrmgr_clock_enables_sva_if

Module : pwrmgr_clock_enables_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_clock_enables_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_clock_enables_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_clock_enables_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_clock_enables_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	30	1	1	100.00
ALWAYS	37	1	1	100.00

29                      
30         1/1            always_comb reset_or_disable = !rst_ni || disable_sva;
           Tests:       T1 T2 T3 
31                      
32                        sequence transitionUp_S; slow_state == pwrmgr_pkg::SlowPwrStateReqPwrUp; endsequence
33                      
34                        sequence transitionDown_S; slow_state == pwrmgr_pkg::SlowPwrStatePwrClampOn; endsequence
35                      
36                        bit fast_is_active;
37         1/1            always_comb fast_is_active = fast_state == pwrmgr_pkg::FastPwrStateActive;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : pwrmgr_clock_enables_sva_if

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       30
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T82,T50

 LINE       37
 EXPRESSION (fast_state == FastPwrStateActive)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_clock_enables_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CoreClkPwrDown_A	4215508	10575	0	0
CoreClkPwrUp_A	4215508	147461	0	0
IoClkPwrDown_A	4215508	10575	0	0
IoClkPwrUp_A	4215508	147461	0	0
UsbClkActive_A	4215508	2698	0	0
UsbClkPwrDown_A	4215508	10575	0	0
UsbClkPwrUp_A	4215508	147461	0	0

CoreClkPwrDown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4215508	10575	0	0
T1	220	1	0	0
T2	395	0	0	0
T3	2328	9	0	0
T4	2249	1	0	0
T5	2788	7	0	0
T6	127	0	0	0
T7	208	0	0	0
T8	160	0	0	0
T9	327	0	0	0
T10	718	0	0	0
T14	0	26	0	0
T15	0	20	0	0
T31	0	1	0	0
T33	0	8	0	0
T34	0	4	0	0
T40	0	9	0	0

CoreClkPwrUp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4215508	147461	0	0
T1	220	7	0	0
T2	395	0	0	0
T3	2328	139	0	0
T4	2249	9	0	0
T5	2788	76	0	0
T6	127	0	0	0
T7	208	0	0	0
T8	160	0	0	0
T9	327	0	0	0
T10	718	0	0	0
T14	0	202	0	0
T15	0	276	0	0
T31	0	13	0	0
T33	0	118	0	0
T34	0	34	0	0
T40	0	71	0	0

IoClkPwrDown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4215508	10575	0	0
T1	220	1	0	0
T2	395	0	0	0
T3	2328	9	0	0
T4	2249	1	0	0
T5	2788	7	0	0
T6	127	0	0	0
T7	208	0	0	0
T8	160	0	0	0
T9	327	0	0	0
T10	718	0	0	0
T14	0	26	0	0
T15	0	20	0	0
T31	0	1	0	0
T33	0	8	0	0
T34	0	4	0	0
T40	0	9	0	0

IoClkPwrUp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4215508	147461	0	0
T1	220	7	0	0
T2	395	0	0	0
T3	2328	139	0	0
T4	2249	9	0	0
T5	2788	76	0	0
T6	127	0	0	0
T7	208	0	0	0
T8	160	0	0	0
T9	327	0	0	0
T10	718	0	0	0
T14	0	202	0	0
T15	0	276	0	0
T31	0	13	0	0
T33	0	118	0	0
T34	0	34	0	0
T40	0	71	0	0

UsbClkActive_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4215508	2698	0	0
T4	2249	1	0	0
T5	2788	0	0	0
T6	127	1	0	0
T7	208	0	0	0
T8	160	0	0	0
T9	327	0	0	0
T10	718	0	0	0
T11	443	0	0	0
T14	5994	1	0	0
T15	0	2	0	0
T16	0	5	0	0
T17	0	11	0	0
T36	0	2	0	0
T38	0	1	0	0
T40	1337	1	0	0
T85	0	1	0	0

UsbClkPwrDown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4215508	10575	0	0
T1	220	1	0	0
T2	395	0	0	0
T3	2328	9	0	0
T4	2249	1	0	0
T5	2788	7	0	0
T6	127	0	0	0
T7	208	0	0	0
T8	160	0	0	0
T9	327	0	0	0
T10	718	0	0	0
T14	0	26	0	0
T15	0	20	0	0
T31	0	1	0	0
T33	0	8	0	0
T34	0	4	0	0
T40	0	9	0	0

UsbClkPwrUp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4215508	147461	0	0
T1	220	7	0	0
T2	395	0	0	0
T3	2328	139	0	0
T4	2249	9	0	0
T5	2788	76	0	0
T6	127	0	0	0
T7	208	0	0	0
T8	160	0	0	0
T9	327	0	0	0
T10	718	0	0	0
T14	0	202	0	0
T15	0	276	0	0
T31	0	13	0	0
T33	0	118	0	0
T34	0	34	0	0
T40	0	71	0	0