Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	17809161	14130	0	0
intr_enable_rd_A	17809161	34888	0	0
reset_en_rd_A	17809161	1112	0	0
reset_en_regwen_rd_A	17809161	1055	0	0
wake_info_capture_dis_rd_A	17809161	1011	0	0
wakeup_en_rd_A	17809161	1651	0	0
wakeup_en_regwen_rd_A	17809161	1059	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17809161	14130	0	0
T23	276117	134	0	0
T24	0	56	0	0
T25	0	23	0	0
T54	0	41	0	0
T55	0	184	0	0
T60	0	68	0	0
T86	0	164	0	0
T87	0	20	0	0
T144	0	24	0	0
T145	0	12	0	0
T146	1472	0	0	0
T147	10604	0	0	0
T148	2029	0	0	0
T149	18945	0	0	0
T150	1543	0	0	0
T151	4552	0	0	0
T152	3327	0	0	0
T153	1193	0	0	0
T154	3682	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17809161	34888	0	0
T5	13061	66	0	0
T6	1533	0	0	0
T7	2420	0	0	0
T8	1830	0	0	0
T9	3108	0	0	0
T10	4903	54	0	0
T11	9375	0	0	0
T14	54459	188	0	0
T15	24912	132	0	0
T27	0	15	0	0
T33	0	61	0	0
T36	0	15	0	0
T37	0	56	0	0
T40	14168	60	0	0
T83	0	175	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17809161	1112	0	0
T24	110786	45	0	0
T25	180697	18	0	0
T67	0	20	0	0
T88	0	32	0	0
T110	0	3	0	0
T155	0	6	0	0
T156	0	7	0	0
T157	0	7	0	0
T158	0	2	0	0
T159	0	8	0	0
T160	25532	0	0	0
T161	1346	0	0	0
T162	4512	0	0	0
T163	1077	0	0	0
T164	9869	0	0	0
T165	13536	0	0	0
T166	5865	0	0	0
T167	57188	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17809161	1055	0	0
T24	110786	24	0	0
T25	180697	3	0	0
T67	0	37	0	0
T88	0	36	0	0
T110	0	3	0	0
T155	0	8	0	0
T156	0	3	0	0
T157	0	5	0	0
T158	0	9	0	0
T160	25532	0	0	0
T161	1346	0	0	0
T162	4512	0	0	0
T163	1077	0	0	0
T164	9869	0	0	0
T165	13536	0	0	0
T166	5865	0	0	0
T167	57188	0	0	0
T168	0	7	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17809161	1011	0	0
T24	110786	24	0	0
T25	180697	14	0	0
T67	0	17	0	0
T88	0	30	0	0
T155	0	6	0	0
T156	0	16	0	0
T157	0	15	0	0
T158	0	5	0	0
T159	0	20	0	0
T160	25532	0	0	0
T161	1346	0	0	0
T162	4512	0	0	0
T163	1077	0	0	0
T164	9869	0	0	0
T165	13536	0	0	0
T166	5865	0	0	0
T167	57188	0	0	0
T168	0	1	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17809161	1651	0	0
T24	110786	26	0	0
T25	180697	6	0	0
T67	0	3	0	0
T88	0	24	0	0
T110	0	14	0	0
T155	0	7	0	0
T156	0	6	0	0
T157	0	4	0	0
T158	0	1	0	0
T160	25532	0	0	0
T161	1346	0	0	0
T162	4512	0	0	0
T163	1077	0	0	0
T164	9869	0	0	0
T165	13536	0	0	0
T166	5865	0	0	0
T167	57188	0	0	0
T168	0	10	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17809161	1059	0	0
T24	110786	54	0	0
T25	180697	12	0	0
T67	0	19	0	0
T88	0	45	0	0
T110	0	9	0	0
T155	0	4	0	0
T156	0	4	0	0
T157	0	20	0	0
T159	0	5	0	0
T160	25532	0	0	0
T161	1346	0	0	0
T162	4512	0	0	0
T163	1077	0	0	0
T164	9869	0	0	0
T165	13536	0	0	0
T166	5865	0	0	0
T167	57188	0	0	0
T168	0	2	0	0