Line Coverage for Module : pwrmgr_fsm
Cond Coverage for Module : pwrmgr_fsm
FSM Coverage for Module : pwrmgr_fsm
State, Transition and Sequence Details for FSM :: state_q
Branch Coverage for Module : pwrmgr_fsm
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Assert Coverage for Module : pwrmgr_fsm
Assertion Details
AlwaysOnIndex_A
u_state_regs_A
| Line No. | Total | Covered | Percent | |
|---|---|---|---|---|
| TOTAL | 149 | 149 | 100.00 | |
| CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 129 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
| ALWAYS | 157 | 17 | 17 | 100.00 |
| ALWAYS | 179 | 3 | 3 | 100.00 |
| ALWAYS | 182 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 197 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 233 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 250 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 256 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 258 | 1 | 1 | 100.00 |
| ALWAYS | 261 | 97 | 97 | 100.00 |
| CONT_ASSIGN | 497 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 498 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 499 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 502 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 504 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 508 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 509 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 519 | 1 | 1 | 100.00 |
121 122 1/1 assign pd_n_rsts_asserted = pwr_rst_i.rst_lc_src_n[PowerDomains-1:OffDomainSelStart] == '0 & Tests: T1 T2 T3 123 pwr_rst_i.rst_sys_src_n[PowerDomains-1:OffDomainSelStart] == '0; 124 125 logic lc_rsts_valid; 126 1/1 assign lc_rsts_valid = ((rst_lc_req_q & ~pwr_rst_i.rst_lc_src_n) | Tests: T1 T2 T3 127 (~rst_lc_req_q & pwr_rst_i.rst_lc_src_n)) == {PowerDomains{1'b1}}; 128 logic sys_rsts_valid; 129 1/1 assign sys_rsts_valid = ((rst_sys_req_q & ~pwr_rst_i.rst_sys_src_n) | Tests: T1 T2 T3 130 (~rst_sys_req_q & pwr_rst_i.rst_sys_src_n)) == {PowerDomains{1'b1}}; 131 132 1/1 assign all_rsts_asserted = lc_rsts_valid & sys_rsts_valid; Tests: T1 T2 T3 133 134 // Any reset request was asserted. 135 1/1 assign reset_req = |reset_reqs_i; Tests: T1 T2 T3 136 137 // Any peripheral triggererd hardware reset request. 138 1/1 assign hw_rst_req = |reset_reqs_i[NumRstReqs-1:0]; Tests: T1 T2 T3 139 140 // Direct reset request that bypass checks. 141 1/1 assign direct_rst_req = reset_reqs_i[ResetEscIdx] | Tests: T1 T2 T3 142 reset_reqs_i[ResetMainPwrIdx]; 143 144 // Ndm reset request. 145 1/1 assign ndmreset_req = reset_reqs_i[ResetNdmIdx]; Tests: T1 T2 T3 146 147 // Software triggered reset request. 148 1/1 assign sw_rst_req = reset_reqs_i[ResetSwReqIdx]; Tests: T1 T2 T3 149 150 // when in low power path, resets are controlled by domain power down 151 // when in reset path, all resets must be asserted 152 // when the reset cause is something else, it is invalid 153 1/1 assign reset_valid = reset_cause_q == LowPwrEntry ? main_pd_ni | pd_n_rsts_asserted : Tests: T1 T2 T3 154 reset_cause_q == HwReq ? all_rsts_asserted : 1'b0; 155 156 always_ff @(posedge clk_i or negedge rst_ni) begin 157 1/1 if (!rst_ni) begin Tests: T1 T2 T3 158 1/1 ack_pwrup_q <= 1'b0; Tests: T1 T2 T3 159 1/1 req_pwrdn_q <= 1'b0; Tests: T1 T2 T3 160 1/1 reset_ongoing_q <= 1'b0; Tests: T1 T2 T3 161 1/1 ip_clk_en_q <= 1'b0; Tests: T1 T2 T3 162 1/1 rst_lc_req_q <= {PowerDomains{1'b1}}; Tests: T1 T2 T3 163 1/1 rst_sys_req_q <= {PowerDomains{1'b1}}; Tests: T1 T2 T3 164 1/1 reset_cause_q <= ResetUndefined; Tests: T1 T2 T3 165 1/1 low_power_q <= 1'b1; Tests: T1 T2 T3 166 end else begin 167 1/1 ack_pwrup_q <= ack_pwrup_d; Tests: T1 T2 T3 168 1/1 req_pwrdn_q <= req_pwrdn_d; Tests: T1 T2 T3 169 1/1 reset_ongoing_q <= reset_ongoing_d; Tests: T1 T2 T3 170 1/1 ip_clk_en_q <= ip_clk_en_d; Tests: T1 T2 T3 171 1/1 rst_lc_req_q <= rst_lc_req_d; Tests: T1 T2 T3 172 1/1 rst_sys_req_q <= rst_sys_req_d; Tests: T1 T2 T3 173 1/1 reset_cause_q <= reset_cause_d; Tests: T1 T2 T3 174 1/1 low_power_q <= low_power_d; Tests: T1 T2 T3 175 end 176 end 177 178 // SEC_CM: FSM.SPARSE179 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, fast_pwr_state_e, FastPwrStateLowPower) Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, fast_pwr_state_e, FastPwrStateLowPower): 179.1 `ifdef SIMULATION 179.2 prim_sparse_fsm_flop #( 179.3 .StateEnumT(fast_pwr_state_e), 179.4 .Width($bits(fast_pwr_state_e)), 179.5 .ResetValue($bits(fast_pwr_state_e)'(FastPwrStateLowPower)), 179.6 .EnableAlertTriggerSVA(1), 179.7 .CustomForceName("state_q") 179.8 ) u_state_regs ( 179.9 .clk_i ( clk_i ), 179.10 .rst_ni ( rst_ni ), 179.11 .state_i ( state_d ), 179.12 .state_o ( ) 179.13 ); 179.14 always_ff @(posedge clk_i or negedge rst_ni) begin 179.15 1/1 if (!rst_ni) begin Tests: T1 T2 T3 179.16 1/1 state_q <= FastPwrStateLowPower; Tests: T1 T2 T3 179.17 end else begin 179.18 1/1 state_q <= state_d; Tests: T1 T2 T3 179.19 end 179.20 end 179.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o)) 179.22 else begin 179.23 `ifdef UVM 179.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 179.25 "../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr_fsm.sv", 179, "", 1); 179.26 `else 179.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__, 179.28 `PRIM_STRINGIFY(u_state_regs_A)); 179.29 `endif 179.30 end 179.31 `else 179.32 prim_sparse_fsm_flop #( 179.33 .StateEnumT(fast_pwr_state_e), 179.34 .Width($bits(fast_pwr_state_e)), 179.35 .ResetValue($bits(fast_pwr_state_e)'(FastPwrStateLowPower)), 179.36 .EnableAlertTriggerSVA(1) 179.37 ) u_state_regs ( 179.38 .clk_i ( `PRIM_FLOP_CLK ), 179.39 .rst_ni ( `PRIM_FLOP_RST ), 179.40 .state_i ( state_d ), 179.41 .state_o ( state_q ) 179.42 ); 179.43 `endif180 181 always_ff @(posedge clk_i or negedge rst_ni) begin 182 1/1 if (!rst_ni) begin Tests: T1 T2 T3 183 1/1 strap_sampled <= 1'b0; Tests: T1 T2 T3 184 1/1 end else if (&rst_sys_req_q) begin Tests: T1 T2 T3 185 1/1 strap_sampled <= 1'b0; Tests: T1 T2 T3 186 1/1 end else if (strap_o) begin Tests: T1 T2 T3 187 1/1 strap_sampled <= 1'b1; Tests: T1 T2 T3 188 end MISSING_ELSE 189 end 190 191 prim_lc_sender u_fetch_en ( 192 .clk_i, 193 .rst_ni, 194 .lc_en_i(fetch_en_d), 195 .lc_en_o(fetch_en_q) 196 ); 197 1/1 assign fetch_en_o = fetch_en_q; Tests: T1 T2 T3 198 199 // Life cycle broadcast may take time to propagate through the system. 200 // The sync below simulates that behavior using the slowest clock in the 201 // system. 202 logic slow_lc_done; 203 logic lc_done; 204 205 prim_flop_2sync #( 206 .Width(1) 207 ) u_slow_sync_lc_done ( 208 .clk_i(clk_slow_i), 209 .rst_ni(rst_slow_ni), 210 .d_i(lc_done_i), 211 .q_o(slow_lc_done) 212 ); 213 214 prim_flop_2sync #( 215 .Width(1) 216 ) u_sync_lc_done ( 217 .clk_i, 218 .rst_ni, 219 .d_i(slow_lc_done), 220 .q_o(lc_done) 221 ); 222 223 224 logic clks_enabled; 225 logic clks_disabled; 226 227 // clocks all enabled computed as follows: 228 // if enable is high, meaning clock is requested to turn on, the status must 229 // also be 1. 230 // if enable is low, meaning clock is not requested to turn on, the status is 231 // don't care. 232 // the bit-wise OR of both conditions must be all true. 233 1/1 assign clks_enabled = ip_clk_en_q && Tests: T1 T2 T3 234 &((ips_clk_en_o & clk_en_status_i) | ~ips_clk_en_o); 235 236 // clocks all disabled is the opposite: 237 // if enable is low the status must also be low. 238 // if enable is high, the status is don't care. 239 // the bit-wise OR of both conditions must be all true. 240 1/1 assign clks_disabled = ~ip_clk_en_q && Tests: T1 T2 T3 241 &((~ips_clk_en_o & ~clk_en_status_i) | ips_clk_en_o); 242 243 244 // rom integrity checks are disabled during TEST / RMA states 245 // During TEST / RMA states, both dft_en and hw_debug_en are On. 246 // During DEV / PROD states, either both signals are Off, or only 247 // hw_debug_en is On 248 249 mubi4_t rom_intg_chk_dis; 250 1/1 assign rom_intg_chk_dis = lc_tx_test_true_strict(lc_tx_and_hi(lc_dft_en_i, lc_hw_debug_en_i)) ? Tests: T1 T2 T3 251 prim_mubi_pkg::MuBi4True : 252 prim_mubi_pkg::MuBi4False; 253 254 mubi4_t rom_intg_chk_done; 255 mubi4_t rom_intg_chk_good; 256 1/1 assign rom_intg_chk_done = mubi4_or_hi(mubi4_and_hi(rom_intg_chk_dis, rom_ctrl_done_i), Tests: T1 T2 T3 257 rom_ctrl_done_i); 258 1/1 assign rom_intg_chk_good = mubi4_or_hi(rom_intg_chk_dis, rom_ctrl_good_i); Tests: T1 T2 T3 259 260 always_comb begin 261 1/1 otp_init = 1'b0; Tests: T1 T2 T3 262 1/1 lc_init = 1'b0; Tests: T1 T2 T3 263 1/1 wkup_o = 1'b0; Tests: T1 T2 T3 264 1/1 fall_through_o = 1'b0; Tests: T1 T2 T3 265 1/1 abort_o = 1'b0; Tests: T1 T2 T3 266 1/1 clr_hint_o = 1'b0; Tests: T1 T2 T3 267 1/1 clr_cfg_lock_o = 1'b0; Tests: T1 T2 T3 268 1/1 strap_o = 1'b0; Tests: T1 T2 T3 269 1/1 clr_slow_req_o = 1'b0; Tests: T1 T2 T3 270 271 1/1 state_d = state_q; Tests: T1 T2 T3 272 1/1 ack_pwrup_d = ack_pwrup_q; Tests: T1 T2 T3 273 1/1 req_pwrdn_d = req_pwrdn_q; Tests: T1 T2 T3 274 1/1 reset_ongoing_d = reset_ongoing_q; Tests: T1 T2 T3 275 1/1 ip_clk_en_d = ip_clk_en_q; Tests: T1 T2 T3 276 1/1 rst_lc_req_d = rst_lc_req_q; Tests: T1 T2 T3 277 1/1 rst_sys_req_d = rst_sys_req_q; Tests: T1 T2 T3 278 1/1 reset_cause_d = reset_cause_q; Tests: T1 T2 T3 279 1/1 low_power_d = low_power_q; Tests: T1 T2 T3 280 1/1 fetch_en_d = fetch_en_q; Tests: T1 T2 T3 281 282 1/1 unique case(state_q) Tests: T1 T2 T3 283 284 FastPwrStateLowPower: begin 285 1/1 if (req_pwrup_i || reset_ongoing_q) begin Tests: T1 T2 T3 286 1/1 state_d = FastPwrStateEnableClocks; Tests: T1 T2 T3 287 end MISSING_ELSE 288 end 289 290 FastPwrStateEnableClocks: begin 291 1/1 ip_clk_en_d = 1'b1; Tests: T1 T2 T3 292 1/1 if (clks_enabled) begin Tests: T1 T2 T3 293 1/1 state_d = FastPwrStateReleaseLcRst; Tests: T1 T2 T3 294 end MISSING_ELSE 295 end 296 297 FastPwrStateReleaseLcRst: begin 298 1/1 rst_lc_req_d = '0; // release rst_lc_n for all power domains Tests: T1 T2 T3 299 1/1 rst_sys_req_d = '0; // release rst_sys_n for all power domains Tests: T1 T2 T3 300 // once all resets are released continue to otp initialization 301 1/1 if (&pwr_rst_i.rst_lc_src_n) begin Tests: T1 T2 T3 302 1/1 state_d = FastPwrStateOtpInit; Tests: T1 T2 T3 303 end MISSING_ELSE 304 end 305 306 FastPwrStateOtpInit: begin 307 1/1 otp_init = 1'b1; Tests: T1 T2 T3 308 309 1/1 if (otp_done_i) begin Tests: T1 T2 T3 310 1/1 state_d = FastPwrStateLcInit; Tests: T1 T2 T3 311 end MISSING_ELSE 312 end 313 314 FastPwrStateLcInit: begin 315 1/1 lc_init = 1'b1; Tests: T1 T2 T3 316 317 1/1 if (lc_done) begin Tests: T1 T2 T3 318 1/1 state_d = FastPwrStateAckPwrUp; Tests: T1 T2 T3 319 320 end MISSING_ELSE 321 end 322 323 FastPwrStateAckPwrUp: begin 324 // only ack the slow_fsm if we actually transitioned through it 325 1/1 ack_pwrup_d = !reset_ongoing_q; Tests: T1 T2 T3 326 327 // wait for request power up to drop relative to ack 328 1/1 if (!req_pwrup_i || reset_ongoing_q) begin Tests: T1 T2 T3 329 1/1 ack_pwrup_d = 1'b0; Tests: T1 T2 T3 330 1/1 clr_cfg_lock_o = 1'b1; Tests: T1 T2 T3 331 // generate a wakeup interrupt if we intended to go to low power 332 // and we were woken from low power with a wakeup and not reset 333 1/1 wkup_o = (pwrup_cause_i == Wake) & (reset_cause_q == LowPwrEntry); Tests: T1 T2 T3 334 // This constitutes the end of a reset cycle 335 1/1 reset_ongoing_d = 1'b0; Tests: T1 T2 T3 336 1/1 state_d = FastPwrStateStrap; Tests: T1 T2 T3 337 end MISSING_ELSE 338 end 339 340 FastPwrStateStrap: begin 341 1/1 strap_o = ~strap_sampled; Tests: T1 T2 T3 342 1/1 state_d = FastPwrStateRomCheckDone; Tests: T1 T2 T3 343 end 344 345 FastPwrStateRomCheckDone: begin 346 // zero outgoing low power indication 347 1/1 low_power_d = '0; Tests: T1 T2 T3 348 1/1 reset_cause_d = ResetNone; Tests: T1 T2 T3 349 350 // When done is observed, advance to good check 351 1/1 if (mubi4_test_true_strict(rom_intg_chk_done)) begin Tests: T1 T2 T3 352 1/1 state_d = FastPwrStateRomCheckGood; Tests: T1 T2 T3 353 end MISSING_ELSE 354 end 355 356 FastPwrStateRomCheckGood: begin 357 1/1 if (mubi4_test_true_strict(rom_intg_chk_good)) begin Tests: T1 T2 T3 358 1/1 state_d = FastPwrStateActive; Tests: T1 T2 T3 359 end MISSING_ELSE 360 end 361 362 FastPwrStateActive: begin 363 // only in active state, allow processor to execute 364 1/1 fetch_en_d = lc_ctrl_pkg::On; Tests: T1 T2 T3 365 366 // when handling reset request or low power entry of any 367 // kind, stop processor from fetching 368 1/1 if (reset_req || low_power_entry_i) begin Tests: T1 T2 T3 369 1/1 fetch_en_d = lc_ctrl_pkg::Off; Tests: T1 T2 T3 370 1/1 reset_cause_d = ResetUndefined; Tests: T1 T2 T3 371 1/1 state_d = FastPwrStateDisClks; Tests: T1 T2 T3 372 end MISSING_ELSE 373 end 374 375 FastPwrStateDisClks: begin 376 1/1 ip_clk_en_d = 1'b0; Tests: T1 T2 T3 377 378 1/1 if (clks_disabled) begin Tests: T1 T2 T3 379 1/1 state_d = reset_req ? FastPwrStateNvmShutDown : FastPwrStateFallThrough; Tests: T1 T2 T3 380 1/1 low_power_d = ~reset_req; Tests: T1 T2 T3 381 end else begin 382 // escalation was received, skip all handshaking and directly reset 383 1/1 state_d = direct_rst_req ? FastPwrStateNvmShutDown : state_q; Tests: T1 T2 T3 384 1/1 low_power_d = ~reset_req; Tests: T1 T2 T3 385 end 386 end 387 388 // Low Power Path 389 FastPwrStateFallThrough: begin 390 1/1 clr_hint_o = 1'b1; Tests: T1 T3 T4 391 392 // The processor was interrupted after it asserted WFI and is executing again 393 1/1 if (!low_power_entry_i) begin Tests: T1 T3 T4 394 1/1 ip_clk_en_d = 1'b1; Tests: T16 T17 T26 395 1/1 wkup_o = 1'b1; Tests: T16 T17 T26 396 1/1 fall_through_o = 1'b1; Tests: T16 T17 T26 397 1/1 state_d = FastPwrStateRomCheckDone; Tests: T16 T17 T26 398 end else begin 399 1/1 state_d = FastPwrStateNvmIdleChk; Tests: T1 T3 T4 400 end 401 end 402 403 FastPwrStateNvmIdleChk: begin 404 405 1/1 if (otp_idle_i && lc_idle_i && flash_idle_i) begin Tests: T1 T3 T4 406 1/1 state_d = FastPwrStateLowPowerPrep; Tests: T1 T3 T4 407 end else begin 408 1/1 ip_clk_en_d = 1'b1; Tests: T6 T16 T17 409 1/1 wkup_o = 1'b1; Tests: T6 T16 T17 410 1/1 abort_o = 1'b1; Tests: T6 T16 T17 411 1/1 state_d = FastPwrStateRomCheckDone; Tests: T6 T16 T17 412 end 413 end 414 415 FastPwrStateLowPowerPrep: begin 416 // reset cause is set only if main power domain will be turned off 417 1/1 reset_cause_d = LowPwrEntry; Tests: T1 T3 T4 418 419 // reset non-always-on domains if requested 420 // this includes the clock manager, which implies pwr/rst managers must 421 // be fed directly from the source 422 1/1 for (int i = OffDomainSelStart; i < PowerDomains; i++) begin Tests: T1 T3 T4 423 1/1 rst_lc_req_d[i] = ~main_pd_ni; Tests: T1 T3 T4 424 1/1 rst_sys_req_d[i] = ~main_pd_ni; Tests: T1 T3 T4 425 end 426 427 1/1 if (reset_valid) begin Tests: T1 T3 T4 428 1/1 state_d = FastPwrStateReqPwrDn; Tests: T1 T3 T4 429 end MISSING_ELSE 430 end 431 432 FastPwrStateReqPwrDn: begin 433 1/1 req_pwrdn_d = 1'b1; Tests: T1 T3 T4 434 435 1/1 if (ack_pwrdn_i) begin Tests: T1 T3 T4 436 1/1 req_pwrdn_d = 1'b0; Tests: T1 T3 T4 437 1/1 state_d = FastPwrStateLowPower; Tests: T1 T3 T4 438 end MISSING_ELSE 439 end 440 441 // Reset Path 442 FastPwrStateNvmShutDown: begin 443 1/1 clr_hint_o = 1'b1; Tests: T1 T2 T5 444 1/1 reset_ongoing_d = 1'b1; Tests: T1 T2 T5 445 1/1 state_d = FastPwrStateResetPrep; Tests: T1 T2 T5 446 end 447 448 FastPwrStateResetPrep: begin 449 1/1 reset_cause_d = HwReq; Tests: T1 T2 T5 450 1/1 rst_lc_req_d = {PowerDomains{1'b1}}; Tests: T1 T2 T5 451 1/1 rst_sys_req_d = {PowerDomains{(hw_rst_req | Tests: T1 T2 T5 452 direct_rst_req | 453 sw_rst_req) | 454 (ndmreset_req & 455 lc_ctrl_pkg::lc_tx_test_false_loose(lc_hw_debug_en_i))}}; 456 457 458 1/1 state_d = FastPwrStateResetWait; Tests: T1 T2 T5 459 end 460 461 FastPwrStateResetWait: begin 462 1/1 rst_lc_req_d = {PowerDomains{1'b1}}; Tests: T1 T2 T5 463 1/1 clr_slow_req_o = reset_reqs_i[ResetMainPwrIdx]; Tests: T1 T2 T5 464 // The main power reset request is checked here specifically because it is 465 // the only reset request in the system that operates on the POR domain. 466 // This has to be the case since it would otherwise not be able to monitor 467 // the non-always-on domains. 468 // 469 // As a result of this, the normal reset process does not automatically 470 // wipe out the reset request, so we specifically clear it and wait for it to be 471 // cleared before proceeding. This also implies if the system is under a persistent 472 // glitch, or if someone just turned off the power before pwrmgr turns it off itself, 473 // we will stay stuck here and perpetually hold the system in reset. 474 1/1 if (reset_valid && !reset_reqs_i[ResetMainPwrIdx]) begin Tests: T1 T2 T5 475 1/1 state_d = FastPwrStateLowPower; Tests: T1 T2 T5 476 end MISSING_ELSE 477 end 478 479 480 // Terminal state, kill everything 481 // SEC_CM: FSM.TERMINAL 482 default: begin 483 rst_lc_req_d = {PowerDomains{1'b1}}; 484 rst_sys_req_d = {PowerDomains{1'b1}}; 485 ip_clk_en_d = 1'b0; 486 end 487 endcase // unique case (state_q) 488 489 1/1 if (fsm_invalid_i) begin Tests: T1 T2 T3 490 // the slow fsm is completely out of sync, transition to terminal state 491 1/1 state_d = FastPwrStateInvalid; Tests: T45 T28 T20 492 end MISSING_ELSE 493 494 495 end // always_comb 496 497 1/1 assign ack_pwrup_o = ack_pwrup_q; Tests: T1 T2 T3 498 1/1 assign req_pwrdn_o = req_pwrdn_q; Tests: T1 T2 T3 499 1/1 assign low_power_o = low_power_q; Tests: T1 T2 T3 500 501 1/1 assign pwr_rst_o.rst_lc_req = rst_lc_req_q; Tests: T1 T2 T3 502 1/1 assign pwr_rst_o.rst_sys_req = rst_sys_req_q; Tests: T1 T2 T3 503 1/1 assign pwr_rst_o.reset_cause = reset_cause_q; Tests: T1 T2 T3 504 1/1 assign pwr_rst_o.rstreqs = reset_reqs_i[HwResetWidth-1:0]; Tests: T1 T2 T3 505 506 // main and io clocks are only turned on/off as part of normal 507 // power sequence 508 1/1 assign ips_clk_en_o.main_ip_clk_en = ip_clk_en_q; Tests: T1 T2 T3 509 1/1 assign ips_clk_en_o.io_ip_clk_en = ip_clk_en_q; Tests: T1 T2 T3 510 prim_flop #( 511 .Width(1), 512 .ResetValue(1'b0) 513 ) u_usb_ip_clk_en ( 514 .clk_i, 515 .rst_ni, 516 .d_i(ip_clk_en_d & usb_ip_clk_en_i), 517 .q_o(ips_clk_en_o.usb_ip_clk_en) 518 ); 519 1/1 assign usb_ip_clk_status_o = clk_en_status_i.usb_status; Tests: T1 T2 T3
Cond Coverage for Module : pwrmgr_fsm
| Total | Covered | Percent | |
|---|---|---|---|
| Conditions | 64 | 63 | 98.44 |
| Logical | 64 | 63 | 98.44 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 |
LINE 122
EXPRESSION ((pwr_rst_i.rst_lc_src_n[1] == '0) & (pwr_rst_i.rst_sys_src_n[1] == '0))
----------------1---------------- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 122
SUB-EXPRESSION (pwr_rst_i.rst_lc_src_n[1] == '0)
----------------1----------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 122
SUB-EXPRESSION (pwr_rst_i.rst_sys_src_n[1] == '0)
-----------------1----------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 126
EXPRESSION (((rst_lc_req_q & (~pwr_rst_i.rst_lc_src_n)) | ((~rst_lc_req_q) & pwr_rst_i.rst_lc_src_n)) == {pwrmgr_pkg::PowerDomains {1'b1}})
----------------------------------------------------------------1---------------------------------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 129
EXPRESSION (((rst_sys_req_q & (~pwr_rst_i.rst_sys_src_n)) | ((~rst_sys_req_q) & pwr_rst_i.rst_sys_src_n)) == {pwrmgr_pkg::PowerDomains {1'b1}})
------------------------------------------------------------------1-----------------------------------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 132
EXPRESSION (lc_rsts_valid & sys_rsts_valid)
------1------ -------2------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T4 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 141
EXPRESSION (reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx] | reset_reqs_i[pwrmgr_reg_pkg::ResetMainPwrIdx])
--------------------1-------------------- ----------------------2----------------------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T5,T8 |
| 1 | 0 | Covered | T2,T7,T9 |
LINE 153
EXPRESSION ((reset_cause_q == LowPwrEntry) ? (main_pd_ni | pd_n_rsts_asserted) : ((reset_cause_q == HwReq) ? all_rsts_asserted : 1'b0))
---------------1--------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T4 |
LINE 153
SUB-EXPRESSION (reset_cause_q == LowPwrEntry)
---------------1--------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T4 |
LINE 153
SUB-EXPRESSION (main_pd_ni | pd_n_rsts_asserted)
-----1---- ---------2--------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 0 | Covered | T3,T4,T5 |
| 0 | 1 | Covered | T3,T4,T5 |
| 1 | 0 | Covered | T1,T3,T4 |
LINE 153
SUB-EXPRESSION ((reset_cause_q == HwReq) ? all_rsts_asserted : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T5 |
LINE 153
SUB-EXPRESSION (reset_cause_q == HwReq)
------------1-----------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T5 |
LINE 233
EXPRESSION (ip_clk_en_q && ((&((ips_clk_en_o & clk_en_status_i) | (~ips_clk_en_o)))))
-----1----- ----------------------------2----------------------------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 240
EXPRESSION (((~ip_clk_en_q)) && ((&(((~ips_clk_en_o) & (~clk_en_status_i)) | ips_clk_en_o))))
--------1------- ------------------------------2-----------------------------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 285
EXPRESSION (req_pwrup_i || reset_ongoing_q)
-----1----- -------2-------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T5 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 328
EXPRESSION (((!req_pwrup_i)) || reset_ongoing_q)
--------1------- -------2-------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 333
EXPRESSION ((pwrup_cause_i == Wake) & (reset_cause_q == LowPwrEntry))
-----------1----------- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T5,T14,T15 |
| 1 | 0 | Covered | T1,T5,T14 |
| 1 | 1 | Covered | T1,T3,T4 |
LINE 333
SUB-EXPRESSION (pwrup_cause_i == Wake)
-----------1-----------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T4 |
LINE 333
SUB-EXPRESSION (reset_cause_q == LowPwrEntry)
---------------1--------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T4 |
LINE 368
EXPRESSION (reset_req || low_power_entry_i)
----1---- --------2--------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T3,T4 |
| 1 | 0 | Covered | T1,T2,T5 |
LINE 379
EXPRESSION (reset_req ? FastPwrStateNvmShutDown : FastPwrStateFallThrough)
----1----
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T3,T4 |
| 1 | Covered | T1,T2,T5 |
LINE 383
EXPRESSION (direct_rst_req ? FastPwrStateNvmShutDown : state_q)
-------1------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T5,T7 |
LINE 405
EXPRESSION (otp_idle_i && lc_idle_i && flash_idle_i)
-----1---- ----2---- ------3-----
| -1- | -2- | -3- | Status | Tests |
|---|---|---|---|---|
| 0 | 1 | 1 | Covered | T16,T17,T46 |
| 1 | 0 | 1 | Covered | T16,T17,T26 |
| 1 | 1 | 0 | Covered | T6,T17,T47 |
| 1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 474
EXPRESSION (reset_valid && ((!reset_reqs_i[pwrmgr_reg_pkg::ResetMainPwrIdx])))
-----1----- -------------------------2------------------------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T1,T2,T5 |
| 1 | 0 | Covered | T2,T5,T14 |
| 1 | 1 | Covered | T1,T2,T5 |
LINE 513
EXPRESSION (ip_clk_en_d & usb_ip_clk_en_i)
-----1----- -------2-------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T4,T5 |
| 1 | 1 | Covered | T1,T2,T3 |
FSM Coverage for Module : pwrmgr_fsm
| Total | Covered | Percent | ||
|---|---|---|---|---|
| States | 19 | 19 | 100.00 | (Not included in score) |
| Transitions | 39 | 37 | 94.87 | |
| Sequences | 0 | 0 |
State, Transition and Sequence Details for FSM :: state_q
| states | Line No. | Covered | Tests |
| FastPwrStateAckPwrUp | 318 | Covered | T1,T2,T3 |
| FastPwrStateActive | 358 | Covered | T1,T2,T3 |
| FastPwrStateDisClks | 371 | Covered | T1,T2,T3 |
| FastPwrStateEnableClocks | 286 | Covered | T1,T2,T3 |
| FastPwrStateFallThrough | 379 | Covered | T1,T3,T4 |
| FastPwrStateInvalid | 491 | Covered | T45,T28,T20 |
| FastPwrStateLcInit | 310 | Covered | T1,T2,T3 |
| FastPwrStateLowPower | 437 | Covered | T1,T2,T3 |
| FastPwrStateLowPowerPrep | 406 | Covered | T1,T3,T4 |
| FastPwrStateNvmIdleChk | 399 | Covered | T1,T3,T4 |
| FastPwrStateNvmShutDown | 379 | Covered | T1,T2,T5 |
| FastPwrStateOtpInit | 302 | Covered | T1,T2,T3 |
| FastPwrStateReleaseLcRst | 293 | Covered | T1,T2,T3 |
| FastPwrStateReqPwrDn | 428 | Covered | T1,T3,T4 |
| FastPwrStateResetPrep | 445 | Covered | T1,T2,T5 |
| FastPwrStateResetWait | 458 | Covered | T1,T2,T5 |
| FastPwrStateRomCheckDone | 342 | Covered | T1,T2,T3 |
| FastPwrStateRomCheckGood | 352 | Covered | T1,T2,T3 |
| FastPwrStateStrap | 336 | Covered | T1,T2,T3 |
| transitions | Line No. | Covered | Tests |
| FastPwrStateAckPwrUp->FastPwrStateInvalid | 491 | Covered | T28,T41,T48 |
| FastPwrStateAckPwrUp->FastPwrStateStrap | 336 | Covered | T1,T2,T3 |
| FastPwrStateActive->FastPwrStateDisClks | 371 | Covered | T1,T2,T3 |
| FastPwrStateActive->FastPwrStateInvalid | 491 | Covered | T20,T21,T22 |
| FastPwrStateDisClks->FastPwrStateFallThrough | 379 | Covered | T1,T3,T4 |
| FastPwrStateDisClks->FastPwrStateInvalid | 491 | Covered | T28,T41,T48 |
| FastPwrStateDisClks->FastPwrStateNvmShutDown | 379 | Covered | T1,T2,T5 |
| FastPwrStateEnableClocks->FastPwrStateInvalid | 491 | Covered | T28,T41,T48 |
| FastPwrStateEnableClocks->FastPwrStateReleaseLcRst | 293 | Covered | T1,T2,T3 |
| FastPwrStateFallThrough->FastPwrStateInvalid | 491 | Covered | T45,T49,T50 |
| FastPwrStateFallThrough->FastPwrStateNvmIdleChk | 399 | Covered | T1,T3,T4 |
| FastPwrStateFallThrough->FastPwrStateRomCheckDone | 397 | Covered | T16,T17,T26 |
| FastPwrStateLcInit->FastPwrStateAckPwrUp | 318 | Covered | T1,T2,T3 |
| FastPwrStateLcInit->FastPwrStateInvalid | 491 | Covered | T28,T41,T48 |
| FastPwrStateLowPower->FastPwrStateEnableClocks | 286 | Covered | T1,T2,T3 |
| FastPwrStateLowPower->FastPwrStateInvalid | 491 | Covered | T28,T41,T48 |
| FastPwrStateLowPowerPrep->FastPwrStateInvalid | 491 | Covered | T45,T49,T50 |
| FastPwrStateLowPowerPrep->FastPwrStateReqPwrDn | 428 | Covered | T1,T3,T4 |
| FastPwrStateNvmIdleChk->FastPwrStateInvalid | 491 | Covered | T45,T49,T50 |
| FastPwrStateNvmIdleChk->FastPwrStateLowPowerPrep | 406 | Covered | T1,T3,T4 |
| FastPwrStateNvmIdleChk->FastPwrStateRomCheckDone | 411 | Covered | T6,T16,T17 |
| FastPwrStateNvmShutDown->FastPwrStateInvalid | 491 | Covered | T28,T41,T48 |
| FastPwrStateNvmShutDown->FastPwrStateResetPrep | 445 | Covered | T1,T2,T5 |
| FastPwrStateOtpInit->FastPwrStateInvalid | 491 | Covered | T28,T41,T48 |
| FastPwrStateOtpInit->FastPwrStateLcInit | 310 | Covered | T1,T2,T3 |
| FastPwrStateReleaseLcRst->FastPwrStateInvalid | 491 | Covered | T28,T41,T48 |
| FastPwrStateReleaseLcRst->FastPwrStateOtpInit | 302 | Covered | T1,T2,T3 |
| FastPwrStateReqPwrDn->FastPwrStateInvalid | 491 | Covered | T45,T49,T50 |
| FastPwrStateReqPwrDn->FastPwrStateLowPower | 437 | Covered | T1,T3,T4 |
| FastPwrStateResetPrep->FastPwrStateInvalid | 491 | Covered | T28,T41,T48 |
| FastPwrStateResetPrep->FastPwrStateResetWait | 458 | Covered | T1,T2,T5 |
| FastPwrStateResetWait->FastPwrStateInvalid | 491 | Not Covered | |
| FastPwrStateResetWait->FastPwrStateLowPower | 475 | Covered | T1,T2,T5 |
| FastPwrStateRomCheckDone->FastPwrStateInvalid | 491 | Covered | T28,T41,T48 |
| FastPwrStateRomCheckDone->FastPwrStateRomCheckGood | 352 | Covered | T1,T2,T3 |
| FastPwrStateRomCheckGood->FastPwrStateActive | 358 | Covered | T1,T2,T3 |
| FastPwrStateRomCheckGood->FastPwrStateInvalid | 491 | Not Covered | |
| FastPwrStateStrap->FastPwrStateInvalid | 491 | Covered | T28,T41,T48 |
| FastPwrStateStrap->FastPwrStateRomCheckDone | 342 | Covered | T1,T2,T3 |
Branch Coverage for Module : pwrmgr_fsm
| Line No. | Total | Covered | Percent | |
|---|---|---|---|---|
| Branches | 49 | 49 | 100.00 | |
| TERNARY | 153 | 3 | 3 | 100.00 |
| IF | 157 | 2 | 2 | 100.00 |
| IF | 179 | 2 | 2 | 100.00 |
| IF | 182 | 4 | 4 | 100.00 |
| CASE | 282 | 36 | 36 | 100.00 |
| IF | 489 | 2 | 2 | 100.00 |
153 assign reset_valid = reset_cause_q == LowPwrEntry ? main_pd_ni | pd_n_rsts_asserted : -1- ==> 154 reset_cause_q == HwReq ? all_rsts_asserted : 1'b0; -2- ==> ==>
Branches:
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 1 | - | Covered | T1,T3,T4 |
| 0 | 1 | Covered | T1,T2,T5 |
| 0 | 0 | Covered | T1,T2,T3 |
157 if (!rst_ni) begin -1- 158 ack_pwrup_q <= 1'b0; ==> 159 req_pwrdn_q <= 1'b0; 160 reset_ongoing_q <= 1'b0; 161 ip_clk_en_q <= 1'b0; 162 rst_lc_req_q <= {PowerDomains{1'b1}}; 163 rst_sys_req_q <= {PowerDomains{1'b1}}; 164 reset_cause_q <= ResetUndefined; 165 low_power_q <= 1'b1; 166 end else begin 167 ack_pwrup_q <= ack_pwrup_d; ==>
Branches:
| -1- | Status | Tests |
|---|---|---|
| 1 | Covered | T1,T2,T3 |
| 0 | Covered | T1,T2,T3 |
179 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, fast_pwr_state_e, FastPwrStateLowPower) -1- ==> ==>
Branches:
| -1- | Status | Tests |
|---|---|---|
| 1 | Covered | T1,T2,T3 |
| 0 | Covered | T1,T2,T3 |
182 if (!rst_ni) begin -1- 183 strap_sampled <= 1'b0; ==> 184 end else if (&rst_sys_req_q) begin -2- 185 strap_sampled <= 1'b0; ==> 186 end else if (strap_o) begin -3- 187 strap_sampled <= 1'b1; ==> 188 end MISSING_ELSE ==>
Branches:
| -1- | -2- | -3- | Status | Tests |
|---|---|---|---|---|
| 1 | - | - | Covered | T1,T2,T3 |
| 0 | 1 | - | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | Covered | T1,T2,T3 |
282 unique case(state_q) -1- 283 284 FastPwrStateLowPower: begin 285 if (req_pwrup_i || reset_ongoing_q) begin -2- 286 state_d = FastPwrStateEnableClocks; ==> 287 end MISSING_ELSE ==> 288 end 289 290 FastPwrStateEnableClocks: begin 291 ip_clk_en_d = 1'b1; 292 if (clks_enabled) begin -3- 293 state_d = FastPwrStateReleaseLcRst; ==> 294 end MISSING_ELSE ==> 295 end 296 297 FastPwrStateReleaseLcRst: begin 298 rst_lc_req_d = '0; // release rst_lc_n for all power domains 299 rst_sys_req_d = '0; // release rst_sys_n for all power domains 300 // once all resets are released continue to otp initialization 301 if (&pwr_rst_i.rst_lc_src_n) begin -4- 302 state_d = FastPwrStateOtpInit; ==> 303 end MISSING_ELSE ==> 304 end 305 306 FastPwrStateOtpInit: begin 307 otp_init = 1'b1; 308 309 if (otp_done_i) begin -5- 310 state_d = FastPwrStateLcInit; ==> 311 end MISSING_ELSE ==> 312 end 313 314 FastPwrStateLcInit: begin 315 lc_init = 1'b1; 316 317 if (lc_done) begin -6- 318 state_d = FastPwrStateAckPwrUp; ==> 319 320 end MISSING_ELSE ==> 321 end 322 323 FastPwrStateAckPwrUp: begin 324 // only ack the slow_fsm if we actually transitioned through it 325 ack_pwrup_d = !reset_ongoing_q; 326 327 // wait for request power up to drop relative to ack 328 if (!req_pwrup_i || reset_ongoing_q) begin -7- 329 ack_pwrup_d = 1'b0; ==> 330 clr_cfg_lock_o = 1'b1; 331 // generate a wakeup interrupt if we intended to go to low power 332 // and we were woken from low power with a wakeup and not reset 333 wkup_o = (pwrup_cause_i == Wake) & (reset_cause_q == LowPwrEntry); 334 // This constitutes the end of a reset cycle 335 reset_ongoing_d = 1'b0; 336 state_d = FastPwrStateStrap; 337 end MISSING_ELSE ==> 338 end 339 340 FastPwrStateStrap: begin 341 strap_o = ~strap_sampled; ==> 342 state_d = FastPwrStateRomCheckDone; 343 end 344 345 FastPwrStateRomCheckDone: begin 346 // zero outgoing low power indication 347 low_power_d = '0; 348 reset_cause_d = ResetNone; 349 350 // When done is observed, advance to good check 351 if (mubi4_test_true_strict(rom_intg_chk_done)) begin -8- 352 state_d = FastPwrStateRomCheckGood; ==> 353 end MISSING_ELSE ==> 354 end 355 356 FastPwrStateRomCheckGood: begin 357 if (mubi4_test_true_strict(rom_intg_chk_good)) begin -9- 358 state_d = FastPwrStateActive; ==> 359 end MISSING_ELSE ==> 360 end 361 362 FastPwrStateActive: begin 363 // only in active state, allow processor to execute 364 fetch_en_d = lc_ctrl_pkg::On; 365 366 // when handling reset request or low power entry of any 367 // kind, stop processor from fetching 368 if (reset_req || low_power_entry_i) begin -10- 369 fetch_en_d = lc_ctrl_pkg::Off; ==> 370 reset_cause_d = ResetUndefined; 371 state_d = FastPwrStateDisClks; 372 end MISSING_ELSE ==> 373 end 374 375 FastPwrStateDisClks: begin 376 ip_clk_en_d = 1'b0; 377 378 if (clks_disabled) begin -11- 379 state_d = reset_req ? FastPwrStateNvmShutDown : FastPwrStateFallThrough; -12- ==> ==> 380 low_power_d = ~reset_req; 381 end else begin 382 // escalation was received, skip all handshaking and directly reset 383 state_d = direct_rst_req ? FastPwrStateNvmShutDown : state_q; -13- ==> ==> 384 low_power_d = ~reset_req; 385 end 386 end 387 388 // Low Power Path 389 FastPwrStateFallThrough: begin 390 clr_hint_o = 1'b1; 391 392 // The processor was interrupted after it asserted WFI and is executing again 393 if (!low_power_entry_i) begin -14- 394 ip_clk_en_d = 1'b1; ==> 395 wkup_o = 1'b1; 396 fall_through_o = 1'b1; 397 state_d = FastPwrStateRomCheckDone; 398 end else begin 399 state_d = FastPwrStateNvmIdleChk; ==> 400 end 401 end 402 403 FastPwrStateNvmIdleChk: begin 404 405 if (otp_idle_i && lc_idle_i && flash_idle_i) begin -15- 406 state_d = FastPwrStateLowPowerPrep; ==> 407 end else begin 408 ip_clk_en_d = 1'b1; ==> 409 wkup_o = 1'b1; 410 abort_o = 1'b1; 411 state_d = FastPwrStateRomCheckDone; 412 end 413 end 414 415 FastPwrStateLowPowerPrep: begin 416 // reset cause is set only if main power domain will be turned off 417 reset_cause_d = LowPwrEntry; 418 419 // reset non-always-on domains if requested 420 // this includes the clock manager, which implies pwr/rst managers must 421 // be fed directly from the source 422 for (int i = OffDomainSelStart; i < PowerDomains; i++) begin 423 rst_lc_req_d[i] = ~main_pd_ni; 424 rst_sys_req_d[i] = ~main_pd_ni; 425 end 426 427 if (reset_valid) begin -16- 428 state_d = FastPwrStateReqPwrDn; ==> 429 end MISSING_ELSE ==> 430 end 431 432 FastPwrStateReqPwrDn: begin 433 req_pwrdn_d = 1'b1; 434 435 if (ack_pwrdn_i) begin -17- 436 req_pwrdn_d = 1'b0; ==> 437 state_d = FastPwrStateLowPower; 438 end MISSING_ELSE ==> 439 end 440 441 // Reset Path 442 FastPwrStateNvmShutDown: begin 443 clr_hint_o = 1'b1; ==> 444 reset_ongoing_d = 1'b1; 445 state_d = FastPwrStateResetPrep; 446 end 447 448 FastPwrStateResetPrep: begin 449 reset_cause_d = HwReq; ==> 450 rst_lc_req_d = {PowerDomains{1'b1}}; 451 rst_sys_req_d = {PowerDomains{(hw_rst_req | 452 direct_rst_req | 453 sw_rst_req) | 454 (ndmreset_req & 455 lc_ctrl_pkg::lc_tx_test_false_loose(lc_hw_debug_en_i))}}; 456 457 458 state_d = FastPwrStateResetWait; 459 end 460 461 FastPwrStateResetWait: begin 462 rst_lc_req_d = {PowerDomains{1'b1}}; 463 clr_slow_req_o = reset_reqs_i[ResetMainPwrIdx]; 464 // The main power reset request is checked here specifically because it is 465 // the only reset request in the system that operates on the POR domain. 466 // This has to be the case since it would otherwise not be able to monitor 467 // the non-always-on domains. 468 // 469 // As a result of this, the normal reset process does not automatically 470 // wipe out the reset request, so we specifically clear it and wait for it to be 471 // cleared before proceeding. This also implies if the system is under a persistent 472 // glitch, or if someone just turned off the power before pwrmgr turns it off itself, 473 // we will stay stuck here and perpetually hold the system in reset. 474 if (reset_valid && !reset_reqs_i[ResetMainPwrIdx]) begin -18- 475 state_d = FastPwrStateLowPower; ==> 476 end MISSING_ELSE ==> 477 end 478 479 480 // Terminal state, kill everything 481 // SEC_CM: FSM.TERMINAL 482 default: begin 483 rst_lc_req_d = {PowerDomains{1'b1}}; ==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | -16- | -17- | -18- | Status | Tests |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| FastPwrStateLowPower | 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | Covered | T1,T2,T3 |
| FastPwrStateLowPower | 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | Covered | T1,T2,T3 |
| FastPwrStateEnableClocks | - | 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | Covered | T1,T2,T3 |
| FastPwrStateEnableClocks | - | 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | Covered | T1,T2,T3 |
| FastPwrStateReleaseLcRst | - | - | 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | Covered | T1,T2,T3 |
| FastPwrStateReleaseLcRst | - | - | 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | Covered | T1,T2,T3 |
| FastPwrStateOtpInit | - | - | - | 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | Covered | T1,T2,T3 |
| FastPwrStateOtpInit | - | - | - | 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | Covered | T1,T2,T3 |
| FastPwrStateLcInit | - | - | - | - | 1 | - | - | - | - | - | - | - | - | - | - | - | - | Covered | T1,T2,T3 |
| FastPwrStateLcInit | - | - | - | - | 0 | - | - | - | - | - | - | - | - | - | - | - | - | Covered | T1,T2,T3 |
| FastPwrStateAckPwrUp | - | - | - | - | - | 1 | - | - | - | - | - | - | - | - | - | - | - | Covered | T1,T2,T3 |
| FastPwrStateAckPwrUp | - | - | - | - | - | 0 | - | - | - | - | - | - | - | - | - | - | - | Covered | T1,T2,T3 |
| FastPwrStateStrap | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | Covered | T1,T2,T3 |
| FastPwrStateRomCheckDone | - | - | - | - | - | - | 1 | - | - | - | - | - | - | - | - | - | - | Covered | T1,T2,T3 |
| FastPwrStateRomCheckDone | - | - | - | - | - | - | 0 | - | - | - | - | - | - | - | - | - | - | Covered | T5,T14,T15 |
| FastPwrStateRomCheckGood | - | - | - | - | - | - | - | 1 | - | - | - | - | - | - | - | - | - | Covered | T1,T2,T3 |
| FastPwrStateRomCheckGood | - | - | - | - | - | - | - | 0 | - | - | - | - | - | - | - | - | - | Covered | T13,T38,T27 |
| FastPwrStateActive | - | - | - | - | - | - | - | - | 1 | - | - | - | - | - | - | - | - | Covered | T1,T2,T3 |
| FastPwrStateActive | - | - | - | - | - | - | - | - | 0 | - | - | - | - | - | - | - | - | Covered | T1,T2,T3 |
| FastPwrStateDisClks | - | - | - | - | - | - | - | - | - | 1 | 1 | - | - | - | - | - | - | Covered | T1,T2,T5 |
| FastPwrStateDisClks | - | - | - | - | - | - | - | - | - | 1 | 0 | - | - | - | - | - | - | Covered | T1,T3,T4 |
| FastPwrStateDisClks | - | - | - | - | - | - | - | - | - | 0 | - | 1 | - | - | - | - | - | Covered | T2,T5,T7 |
| FastPwrStateDisClks | - | - | - | - | - | - | - | - | - | 0 | - | 0 | - | - | - | - | - | Covered | T1,T2,T3 |
| FastPwrStateFallThrough | - | - | - | - | - | - | - | - | - | - | - | - | 1 | - | - | - | - | Covered | T16,T17,T26 |
| FastPwrStateFallThrough | - | - | - | - | - | - | - | - | - | - | - | - | 0 | - | - | - | - | Covered | T1,T3,T4 |
| FastPwrStateNvmIdleChk | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | - | - | - | Covered | T1,T3,T4 |
| FastPwrStateNvmIdleChk | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | - | - | - | Covered | T6,T16,T17 |
| FastPwrStateLowPowerPrep | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | - | - | Covered | T1,T3,T4 |
| FastPwrStateLowPowerPrep | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | - | - | Covered | T1,T3,T4 |
| FastPwrStateReqPwrDn | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | - | Covered | T1,T3,T4 |
| FastPwrStateReqPwrDn | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | - | Covered | T1,T3,T4 |
| FastPwrStateNvmShutDown | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | Covered | T1,T2,T5 |
| FastPwrStateResetPrep | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | Covered | T1,T2,T5 |
| FastPwrStateResetWait | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | Covered | T1,T2,T5 |
| FastPwrStateResetWait | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | Covered | T1,T2,T5 |
| default | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | Covered | T45,T28,T20 |
489 if (fsm_invalid_i) begin -1- 490 // the slow fsm is completely out of sync, transition to terminal state 491 state_d = FastPwrStateInvalid; ==> 492 end MISSING_ELSE ==>
Branches:
| -1- | Status | Tests |
|---|---|---|
| 1 | Covered | T45,T28,T20 |
| 0 | Covered | T1,T2,T3 |
Assert Coverage for Module : pwrmgr_fsm
| Total | Attempted | Percent | Succeeded/Matched | Percent | |
|---|---|---|---|---|---|
| Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
| Cover properties | 0 | 0 | 0 | ||
| Cover sequences | 0 | 0 | 0 | ||
| Total | 2 | 2 | 100.00 | 2 | 100.00 |
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
| AlwaysOnIndex_A | 906 | 906 | 0 | 0 |
| u_state_regs_A | 17249266 | 16827331 | 0 | 0 |
AlwaysOnIndex_A
| Name | Attempts | Real Successes | Failures | Incomplete |
|---|---|---|---|---|
| Total | 906 | 906 | 0 | 0 |
| T1 | 1 | 1 | 0 | 0 |
| T2 | 1 | 1 | 0 | 0 |
| T3 | 1 | 1 | 0 | 0 |
| T4 | 1 | 1 | 0 | 0 |
| T5 | 1 | 1 | 0 | 0 |
| T6 | 1 | 1 | 0 | 0 |
| T7 | 1 | 1 | 0 | 0 |
| T8 | 1 | 1 | 0 | 0 |
| T9 | 1 | 1 | 0 | 0 |
| T10 | 1 | 1 | 0 | 0 |
u_state_regs_A
| Name | Attempts | Real Successes | Failures | Incomplete |
|---|---|---|---|---|
| Total | 17249266 | 16827331 | 0 | 0 |
| T1 | 2538 | 2463 | 0 | 0 |
| T2 | 2514 | 2360 | 0 | 0 |
| T3 | 4942 | 4867 | 0 | 0 |
| T4 | 12021 | 11922 | 0 | 0 |
| T5 | 13061 | 12952 | 0 | 0 |
| T6 | 1533 | 1437 | 0 | 0 |
| T7 | 2420 | 2267 | 0 | 0 |
| T8 | 1830 | 1632 | 0 | 0 |
| T9 | 3108 | 2648 | 0 | 0 |
| T10 | 4903 | 4811 | 0 | 0 |