Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	51747798	112154	0	0
StatusRise_A	51747798	125646	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51747798	112154	0	0
T1	7614	6	0	0
T2	7542	24	0	0
T3	14826	39	0	0
T4	36063	40	0	0
T5	39183	73	0	0
T6	4599	4	0	0
T7	7260	3	0	0
T8	5490	0	0	0
T9	9324	0	0	0
T10	14709	9	0	0
T11	0	6	0	0
T40	0	36	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51747798	125646	0	0
T1	7614	9	0	0
T2	7542	30	0	0
T3	14826	42	0	0
T4	36063	42	0	0
T5	39183	78	0	0
T6	4599	6	0	0
T7	7260	9	0	0
T8	5490	6	0	0
T9	9324	18	0	0
T10	14709	12	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	17249266	41607	0	0
StatusRise_A	17249266	46450	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17249266	41607	0	0
T1	2538	2	0	0
T2	2514	8	0	0
T3	4942	15	0	0
T4	12021	16	0	0
T5	13061	30	0	0
T6	1533	1	0	0
T7	2420	1	0	0
T8	1830	0	0	0
T9	3108	0	0	0
T10	4903	3	0	0
T11	0	2	0	0
T40	0	14	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17249266	46450	0	0
T1	2538	3	0	0
T2	2514	10	0	0
T3	4942	16	0	0
T4	12021	17	0	0
T5	13061	32	0	0
T6	1533	2	0	0
T7	2420	3	0	0
T8	1830	2	0	0
T9	3108	6	0	0
T10	4903	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	17249266	41610	0	0
StatusRise_A	17249266	46451	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17249266	41610	0	0
T1	2538	2	0	0
T2	2514	8	0	0
T3	4942	15	0	0
T4	12021	16	0	0
T5	13061	30	0	0
T6	1533	1	0	0
T7	2420	1	0	0
T8	1830	0	0	0
T9	3108	0	0	0
T10	4903	3	0	0
T11	0	2	0	0
T40	0	14	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17249266	46451	0	0
T1	2538	3	0	0
T2	2514	10	0	0
T3	4942	16	0	0
T4	12021	17	0	0
T5	13061	32	0	0
T6	1533	2	0	0
T7	2420	3	0	0
T8	1830	2	0	0
T9	3108	6	0	0
T10	4903	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	17249266	28937	0	0
StatusRise_A	17249266	32745	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17249266	28937	0	0
T1	2538	2	0	0
T2	2514	8	0	0
T3	4942	9	0	0
T4	12021	8	0	0
T5	13061	13	0	0
T6	1533	2	0	0
T7	2420	1	0	0
T8	1830	0	0	0
T9	3108	0	0	0
T10	4903	3	0	0
T11	0	2	0	0
T40	0	8	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17249266	32745	0	0
T1	2538	3	0	0
T2	2514	10	0	0
T3	4942	10	0	0
T4	12021	8	0	0
T5	13061	14	0	0
T6	1533	2	0	0
T7	2420	3	0	0
T8	1830	2	0	0
T9	3108	6	0	0
T10	4903	4	0	0