Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

41                      
42         1/1            always_comb reset_or_disable = !rst_ni || disable_sva;
           Tests:       T1 T2 T3 
43         1/1            always_comb esc_reset_or_disable = !rst_esc_ni || disable_sva;
           Tests:       T1 T2 T3 
44         1/1            always_comb slow_reset_or_disable = !rst_slow_ni || disable_sva;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	17249857	9941	0	0
EscTimeoutStoppedByClReset_A	17249266	2360649	0	0
EscTimeoutTriggersReset_A	4215508	436	0	0
RomAllowActiveState_A	17249266	46039	0	0
RomAllowCheckGoodState_A	17249266	46088	0	0
RomBlockActiveState_A	17249266	31647	0	0
RomBlockCheckGoodState_A	17249266	361632	0	0
RomIntgChkDisFalse_A	17249266	16698398	0	0
RomIntgChkDisTrue_A	17249266	128933	0	0
RstreqChkEsctimeout_A	17249266	3608	0	0
RstreqChkFsmterm_A	17249266	140	0	0
RstreqChkGlbesc_A	17249266	3608	0	0
RstreqChkMainpd_A	17249266	742178	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17249857	9941	0	0
T11	9376	80	0	0
T12	0	4	0	0
T13	4343	0	0	0
T14	54460	0	0	0
T15	24912	0	0	0
T20	7899	0	0	0
T28	6866	0	0	0
T31	1186	0	0	0
T32	1174	0	0	0
T33	8393	0	0	0
T42	0	112	0	0
T45	2942	0	0	0
T115	0	510	0	0
T147	0	407	0	0
T169	0	34	0	0
T170	0	25	0	0
T171	0	216	0	0
T172	0	27	0	0
T173	0	16	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17249266	2360649	0	0
T1	2538	33	0	0
T2	2514	242	0	0
T3	4942	521	0	0
T4	12021	4083	0	0
T5	13061	2654	0	0
T6	1533	0	0	0
T7	2420	12	0	0
T8	1830	0	0	0
T9	3108	42	0	0
T10	4903	35	0	0
T11	0	22	0	0
T40	0	1566	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4215508	436	0	0
T7	208	3	0	0
T8	160	0	0	0
T9	327	0	0	0
T10	718	0	0	0
T11	443	5	0	0
T12	0	3	0	0
T13	337	0	0	0
T14	5994	0	0	0
T15	9413	0	0	0
T40	1337	0	0	0
T42	0	6	0	0
T45	282	0	0	0
T111	0	4	0	0
T115	0	6	0	0
T169	0	3	0	0
T170	0	7	0	0
T171	0	6	0	0
T172	0	2	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17249266	46039	0	0
T1	2538	3	0	0
T2	2514	10	0	0
T3	4942	16	0	0
T4	12021	17	0	0
T5	13061	32	0	0
T6	1533	2	0	0
T7	2420	3	0	0
T8	1830	2	0	0
T9	3108	6	0	0
T10	4903	4	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17249266	46088	0	0
T1	2538	3	0	0
T2	2514	10	0	0
T3	4942	16	0	0
T4	12021	17	0	0
T5	13061	32	0	0
T6	1533	2	0	0
T7	2420	3	0	0
T8	1830	2	0	0
T9	3108	6	0	0
T10	4903	4	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17249266	31647	0	0
T13	4342	805	0	0
T16	3136	0	0	0
T20	7898	0	0	0
T27	0	149	0	0
T28	6865	0	0	0
T31	1186	0	0	0
T32	1173	0	0	0
T33	8392	0	0	0
T34	12989	0	0	0
T35	4865	0	0	0
T36	8273	0	0	0
T38	0	6	0	0
T114	0	389	0	0
T149	0	29	0	0
T174	0	10	0	0
T175	0	355	0	0
T176	0	7	0	0
T177	0	1111	0	0
T178	0	7	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17249266	361632	0	0
T5	13061	414	0	0
T6	1533	0	0	0
T7	2420	0	0	0
T8	1830	0	0	0
T9	3108	0	0	0
T10	4903	0	0	0
T11	9375	0	0	0
T13	0	203	0	0
T14	54459	4015	0	0
T15	24912	1264	0	0
T17	0	1127	0	0
T27	0	40	0	0
T33	0	413	0	0
T38	0	1510	0	0
T40	14168	0	0	0
T82	0	23	0	0
T83	0	3658	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17249266	16698398	0	0
T1	2538	2463	0	0
T2	2514	2360	0	0
T3	4942	4867	0	0
T4	12021	11922	0	0
T5	13061	12952	0	0
T6	1533	1437	0	0
T7	2420	2267	0	0
T8	1830	1632	0	0
T9	3108	2648	0	0
T10	4903	4811	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17249266	128933	0	0
T13	4342	532	0	0
T14	54459	1198	0	0
T15	24912	0	0	0
T20	7898	0	0	0
T27	0	629	0	0
T28	6865	0	0	0
T31	1186	0	0	0
T32	1173	0	0	0
T33	8392	0	0	0
T34	12989	0	0	0
T45	2941	0	0	0
T83	0	1041	0	0
T114	0	195	0	0
T175	0	115	0	0
T176	0	740	0	0
T177	0	1428	0	0
T179	0	2881	0	0
T180	0	299	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17249266	3608	0	0
T2	2514	2	0	0
T3	4942	0	0	0
T4	12021	0	0	0
T5	13061	0	0	0
T6	1533	0	0	0
T7	2420	1	0	0
T8	1830	0	0	0
T9	3108	5	0	0
T10	4903	0	0	0
T11	0	2	0	0
T12	0	1	0	0
T13	0	3	0	0
T20	0	10	0	0
T28	0	3	0	0
T39	0	6	0	0
T40	14168	0	0	0
T44	0	2	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17249266	140	0	0
T16	3136	0	0	0
T20	7898	20	0	0
T21	0	40	0	0
T22	0	20	0	0
T29	0	20	0	0
T30	0	40	0	0
T31	1186	0	0	0
T32	1173	0	0	0
T33	8392	0	0	0
T34	12989	0	0	0
T35	4865	0	0	0
T36	8273	0	0	0
T37	5113	0	0	0
T38	20944	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17249266	3608	0	0
T2	2514	2	0	0
T3	4942	0	0	0
T4	12021	0	0	0
T5	13061	0	0	0
T6	1533	0	0	0
T7	2420	1	0	0
T8	1830	0	0	0
T9	3108	5	0	0
T10	4903	0	0	0
T11	0	2	0	0
T12	0	1	0	0
T13	0	3	0	0
T20	0	10	0	0
T28	0	3	0	0
T39	0	6	0	0
T40	14168	0	0	0
T44	0	2	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17249266	742178	0	0
T2	2514	231	0	0
T3	4942	0	0	0
T4	12021	0	0	0
T5	13061	1186	0	0
T6	1533	0	0	0
T7	2420	0	0	0
T8	1830	6	0	0
T9	3108	0	0	0
T10	4903	0	0	0
T13	0	1042	0	0
T14	0	6418	0	0
T15	0	1390	0	0
T28	0	173	0	0
T33	0	523	0	0
T38	0	2161	0	0
T39	0	549	0	0
T40	14168	0	0	0