Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_wakeup_intr_cg_wrap::wakeup_intr_cg

Group : pwrmgr_env_pkg::pwrmgr_wakeup_intr_cg_wrap::wakeup_intr_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

6 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
WakeupAonTimer_intr_cg	100.00	1	100	1	64	64
WakeupDbgCable_intr_cg	100.00	1	100	1	64	64
WakeupPin_intr_cg	100.00	1	100	1	64	64
WakeupSensorCtrl_intr_cg	100.00	1	100	1	64	64
WakeupSysrst_intr_cg	100.00	1	100	1	64	64
WakeupUsb_intr_cg	100.00	1	100	1	64	64

---

Group Instance : WakeupAonTimer_intr_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupAonTimer_intr_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupAonTimer_intr_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
interrupt_cp	2	0	2	100.00	100	1	1	2
status_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupAonTimer_intr_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
interrupt_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupDbgCable_intr_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupDbgCable_intr_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupDbgCable_intr_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
interrupt_cp	2	0	2	100.00	100	1	1	2
status_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupDbgCable_intr_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
interrupt_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupPin_intr_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupPin_intr_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupPin_intr_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
interrupt_cp	2	0	2	100.00	100	1	1	2
status_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupPin_intr_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
interrupt_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupSensorCtrl_intr_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupSensorCtrl_intr_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupSensorCtrl_intr_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
interrupt_cp	2	0	2	100.00	100	1	1	2
status_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupSensorCtrl_intr_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
interrupt_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupSysrst_intr_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupSysrst_intr_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupSysrst_intr_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
interrupt_cp	2	0	2	100.00	100	1	1	2
status_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupSysrst_intr_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
interrupt_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupUsb_intr_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupUsb_intr_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupUsb_intr_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
interrupt_cp	2	0	2	100.00	100	1	1	2
status_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupUsb_intr_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
interrupt_cross	8	0	8	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32073

1

T1

3

T2

2

T3

13

auto[1]

8152

1

T1

1

T2

1

T4

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30693

1

T1

2

T2

2

T3

13

auto[1]

9532

1

T1

2

T2

1

T4

6

---

Summary for Variable status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for status_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22603

1

T1

2

T2

1

T3

8

auto[1]

17622

1

T1

2

T2

2

T3

5

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17640

1

T1

1

T2

2

T3

13

auto[1]

22585

1

T1

3

T2

1

T4

13

---

Summary for Cross interrupt_cross

Samples crossed: enable_cp status_cp wakeup_cp interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for interrupt_cross

Bins

enable_cp

status_cp

wakeup_cp

interrupt_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

10856

1

T1

1

T2

1

T3

8

auto[0]

auto[0]

auto[1]

auto[0]

7866

1

T1

1

T4

6

T5

7

auto[0]

auto[1]

auto[0]

auto[0]

5119

1

T2

1

T3

5

T7

2

auto[0]

auto[1]

auto[1]

auto[0]

2115

1

T5

6

T17

7

T18

12

auto[1]

auto[0]

auto[0]

auto[0]

809

1

T7

2

T16

8

T32

4

auto[1]

auto[0]

auto[1]

auto[0]

3072

1

T4

1

T6

4

T7

1

auto[1]

auto[1]

auto[0]

auto[0]

856

1

T7

4

T16

2

T32

10

auto[1]

auto[1]

auto[1]

auto[1]

3415

1

T1

1

T2

1

T4

3

User Defined Cross Bins for interrupt_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
no_wakeup	0	Excluded
disable_pin	0	Excluded
no_status_pin	0	Excluded
missing_int	0	Excluded

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32052

1

T1

4

T2

2

T3

13

auto[1]

8173

1

T2

1

T4

2

T6

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30693

1

T1

2

T2

2

T3

13

auto[1]

9532

1

T1

2

T2

1

T4

6

---

Summary for Variable status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for status_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22603

1

T1

2

T2

1

T3

8

auto[1]

17622

1

T1

2

T2

2

T3

5

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17640

1

T1

1

T2

2

T3

13

auto[1]

22585

1

T1

3

T2

1

T4

13

---

Summary for Cross interrupt_cross

Samples crossed: enable_cp status_cp wakeup_cp interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for interrupt_cross

Bins

enable_cp

status_cp

wakeup_cp

interrupt_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

10851

1

T1

1

T2

1

T3

8

auto[0]

auto[0]

auto[1]

auto[0]

7802

1

T1

1

T4

6

T5

7

auto[0]

auto[1]

auto[0]

auto[0]

5159

1

T2

1

T3

5

T7

4

auto[0]

auto[1]

auto[1]

auto[0]

2115

1

T5

6

T17

7

T18

12

auto[1]

auto[0]

auto[0]

auto[0]

814

1

T7

2

T32

4

T76

2

auto[1]

auto[0]

auto[1]

auto[0]

3136

1

T4

1

T6

6

T7

4

auto[1]

auto[1]

auto[0]

auto[0]

816

1

T7

2

T16

4

T32

12

auto[1]

auto[1]

auto[1]

auto[1]

3407

1

T2

1

T4

1

T6

8

User Defined Cross Bins for interrupt_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
no_wakeup	0	Excluded
disable_pin	0	Excluded
no_status_pin	0	Excluded
missing_int	0	Excluded

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32042

1

T1

4

T2

3

T3

13

auto[1]

8183

1

T4

4

T6

13

T7

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30693

1

T1

2

T2

2

T3

13

auto[1]

9532

1

T1

2

T2

1

T4

6

---

Summary for Variable status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for status_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22603

1

T1

2

T2

1

T3

8

auto[1]

17622

1

T1

2

T2

2

T3

5

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17640

1

T1

1

T2

2

T3

13

auto[1]

22585

1

T1

3

T2

1

T4

13

---

Summary for Cross interrupt_cross

Samples crossed: enable_cp status_cp wakeup_cp interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for interrupt_cross

Bins

enable_cp

status_cp

wakeup_cp

interrupt_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

10816

1

T1

1

T2

1

T3

8

auto[0]

auto[0]

auto[1]

auto[0]

7787

1

T1

1

T4

6

T5

7

auto[0]

auto[1]

auto[0]

auto[0]

5210

1

T2

1

T3

5

T7

4

auto[0]

auto[1]

auto[1]

auto[0]

2115

1

T5

6

T17

7

T18

12

auto[1]

auto[0]

auto[0]

auto[0]

849

1

T16

2

T32

12

T18

2

auto[1]

auto[0]

auto[1]

auto[0]

3151

1

T4

1

T6

5

T7

3

auto[1]

auto[1]

auto[0]

auto[0]

765

1

T7

2

T16

2

T32

8

auto[1]

auto[1]

auto[1]

auto[1]

3418

1

T4

3

T6

8

T7

4

User Defined Cross Bins for interrupt_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
no_wakeup	0	Excluded
disable_pin	0	Excluded
no_status_pin	0	Excluded
missing_int	0	Excluded

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32088

1

T1

4

T2

3

T3

13

auto[1]

8137

1

T4

3

T6

12

T7

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30693

1

T1

2

T2

2

T3

13

auto[1]

9532

1

T1

2

T2

1

T4

6

---

Summary for Variable status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for status_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22603

1

T1

2

T2

1

T3

8

auto[1]

17622

1

T1

2

T2

2

T3

5

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17640

1

T1

1

T2

2

T3

13

auto[1]

22585

1

T1

3

T2

1

T4

13

---

Summary for Cross interrupt_cross

Samples crossed: enable_cp status_cp wakeup_cp interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for interrupt_cross

Bins

enable_cp

status_cp

wakeup_cp

interrupt_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

10815

1

T1

1

T2

1

T3

8

auto[0]

auto[0]

auto[1]

auto[0]

7846

1

T1

1

T4

6

T5

7

auto[0]

auto[1]

auto[0]

auto[0]

5167

1

T2

1

T3

5

T7

4

auto[0]

auto[1]

auto[1]

auto[0]

2115

1

T5

6

T17

7

T18

12

auto[1]

auto[0]

auto[0]

auto[0]

850

1

T7

2

T16

4

T32

10

auto[1]

auto[0]

auto[1]

auto[0]

3092

1

T4

1

T6

5

T7

3

auto[1]

auto[1]

auto[0]

auto[0]

808

1

T7

2

T16

4

T32

6

auto[1]

auto[1]

auto[1]

auto[1]

3387

1

T4

2

T6

7

T7

3

User Defined Cross Bins for interrupt_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
no_wakeup	0	Excluded
disable_pin	0	Excluded
no_status_pin	0	Excluded
missing_int	0	Excluded

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32066

1

T1

1

T2

3

T3

13

auto[1]

8159

1

T1

3

T4

2

T6

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30693

1

T1

2

T2

2

T3

13

auto[1]

9532

1

T1

2

T2

1

T4

6

---

Summary for Variable status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for status_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22603

1

T1

2

T2

1

T3

8

auto[1]

17622

1

T1

2

T2

2

T3

5

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17640

1

T1

1

T2

2

T3

13

auto[1]

22585

1

T1

3

T2

1

T4

13

---

Summary for Cross interrupt_cross

Samples crossed: enable_cp status_cp wakeup_cp interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for interrupt_cross

Bins

enable_cp

status_cp

wakeup_cp

interrupt_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

10827

1

T1

1

T2

1

T3

8

auto[0]

auto[0]

auto[1]

auto[0]

7814

1

T4

5

T5

7

T6

4

auto[0]

auto[1]

auto[0]

auto[0]

5149

1

T2

1

T3

5

T7

6

auto[0]

auto[1]

auto[1]

auto[0]

2115

1

T5

6

T17

7

T18

12

auto[1]

auto[0]

auto[0]

auto[0]

838

1

T7

2

T32

2

T28

4

auto[1]

auto[0]

auto[1]

auto[0]

3124

1

T1

1

T4

2

T6

4

auto[1]

auto[1]

auto[0]

auto[0]

826

1

T16

4

T32

6

T18

2

auto[1]

auto[1]

auto[1]

auto[1]

3371

1

T1

2

T6

6

T7

2

User Defined Cross Bins for interrupt_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
no_wakeup	0	Excluded
disable_pin	0	Excluded
no_status_pin	0	Excluded
missing_int	0	Excluded

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32105

1

T1

4

T2

2

T3

13

auto[1]

8120

1

T2

1

T4

6

T6

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30693

1

T1

2

T2

2

T3

13

auto[1]

9532

1

T1

2

T2

1

T4

6

---

Summary for Variable status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for status_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22603

1

T1

2

T2

1

T3

8

auto[1]

17622

1

T1

2

T2

2

T3

5

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17640

1

T1

1

T2

2

T3

13

auto[1]

22585

1

T1

3

T2

1

T4

13

---

Summary for Cross interrupt_cross

Samples crossed: enable_cp status_cp wakeup_cp interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for interrupt_cross

Bins

enable_cp

status_cp

wakeup_cp

interrupt_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

10785

1

T1

1

T2

1

T3

8

auto[0]

auto[0]

auto[1]

auto[0]

7921

1

T1

1

T4

3

T5

7

auto[0]

auto[1]

auto[0]

auto[0]

5201

1

T2

1

T3

5

T7

4

auto[0]

auto[1]

auto[1]

auto[0]

2115

1

T5

6

T17

7

T18

12

auto[1]

auto[0]

auto[0]

auto[0]

880

1

T7

2

T32

2

T28

6

auto[1]

auto[0]

auto[1]

auto[0]

3017

1

T4

4

T6

6

T7

5

auto[1]

auto[1]

auto[0]

auto[0]

774

1

T7

2

T16

10

T32

2

auto[1]

auto[1]

auto[1]

auto[1]

3449

1

T2

1

T4

2

T6

5

User Defined Cross Bins for interrupt_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
no_wakeup	0	Excluded
disable_pin	0	Excluded
no_status_pin	0	Excluded
missing_int	0	Excluded