Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	348946	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

143301

1

T1

53

T2

16

T3

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	260796	1			T1	90		T2	31		T3	77
values[0x0]	115682	1			T1	19		T2	6		T3	23
values[0x1]	115769	1			T1	10		T2	4		T3	27

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	275797	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

216450

1

T1

62

T2

23

T3

44

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1993	1			T6	2		T43	2		T32	1
valid_sources[0x01]	1662	1			T1	2		T5	1		T32	2
valid_sources[0x02]	2413	1			T1	2		T32	4		T35	1
valid_sources[0x03]	1441	1			T1	1		T2	1		T4	3
valid_sources[0x04]	1444	1			T1	3		T32	2		T34	2
valid_sources[0x05]	1951	1			T1	1		T16	27		T32	11
valid_sources[0x06]	1315	1			T5	1		T43	3		T35	1
valid_sources[0x07]	1677	1			T4	1		T5	1		T32	3
valid_sources[0x08]	3627	1			T10	1		T14	7		T32	1
valid_sources[0x09]	1980	1			T1	1		T5	2		T43	1
valid_sources[0x0a]	1344	1			T32	3		T18	2		T28	1
valid_sources[0x0b]	2331	1			T35	1		T17	1		T18	5
valid_sources[0x0c]	2647	1			T6	9		T32	12		T18	3
valid_sources[0x0d]	1677	1			T1	1		T35	1		T37	4
valid_sources[0x0e]	1312	1			T5	1		T35	1		T37	2
valid_sources[0x0f]	1713	1			T4	4		T6	4		T16	1
valid_sources[0x10]	1503	1			T5	2		T6	2		T43	2
valid_sources[0x11]	2204	1			T37	1		T17	2		T18	7
valid_sources[0x12]	1750	1			T6	13		T11	1		T43	1
valid_sources[0x13]	1523	1			T31	15		T32	9		T17	3
valid_sources[0x14]	1523	1			T4	3		T5	1		T43	1
valid_sources[0x15]	1490	1			T4	2		T43	8		T17	2
valid_sources[0x16]	1818	1			T4	4		T21	1		T17	1
valid_sources[0x17]	1864	1			T1	2		T32	1		T18	7
valid_sources[0x18]	2482	1			T1	3		T43	3		T17	1
valid_sources[0x19]	1739	1			T2	1		T5	1		T6	5
valid_sources[0x1a]	1564	1			T5	1		T16	17		T35	1
valid_sources[0x1b]	1639	1			T4	1		T6	3		T32	1
valid_sources[0x1c]	1635	1			T1	1		T4	1		T5	3
valid_sources[0x1d]	2464	1			T2	1		T5	1		T43	3
valid_sources[0x1e]	1929	1			T43	1		T16	3		T32	1
valid_sources[0x1f]	1626	1			T1	1		T5	1		T34	1
valid_sources[0x20]	1736	1			T4	14		T5	1		T6	5
valid_sources[0x21]	1624	1			T2	1		T43	1		T35	1
valid_sources[0x22]	1726	1			T1	1		T34	1		T18	1
valid_sources[0x23]	1672	1			T6	1		T32	11		T17	2
valid_sources[0x24]	1640	1			T2	1		T43	1		T16	9
valid_sources[0x25]	2466	1			T8	43		T32	2		T35	1
valid_sources[0x26]	1551	1			T4	2		T5	1		T43	1
valid_sources[0x27]	1621	1			T5	1		T43	1		T17	1
valid_sources[0x28]	1392	1			T2	1		T43	7		T31	13
valid_sources[0x29]	2142	1			T5	1		T43	1		T17	1
valid_sources[0x2a]	1689	1			T5	1		T43	1		T32	17
valid_sources[0x2b]	1965	1			T1	4		T4	1		T5	1
valid_sources[0x2c]	2568	1			T6	15		T43	3		T16	5
valid_sources[0x2d]	1574	1			T43	1		T17	1		T28	10
valid_sources[0x2e]	1584	1			T32	5		T17	3		T28	7
valid_sources[0x2f]	1613	1			T4	1		T5	1		T32	4
valid_sources[0x30]	3217	1			T4	1		T5	1		T43	6
valid_sources[0x31]	2112	1			T43	3		T32	3		T34	1
valid_sources[0x32]	1611	1			T1	1		T43	1		T38	1
valid_sources[0x33]	1510	1			T1	1		T4	3		T5	2
valid_sources[0x34]	2319	1			T4	2		T33	27		T35	1
valid_sources[0x35]	1401	1			T1	2		T16	30		T38	1
valid_sources[0x36]	4972	1			T1	2		T2	1		T4	3
valid_sources[0x37]	2449	1			T4	1		T43	5		T35	2
valid_sources[0x38]	2820	1			T1	2		T16	46		T32	5
valid_sources[0x39]	1575	1			T1	1		T6	9		T17	6
valid_sources[0x3a]	2331	1			T1	2		T5	1		T43	3
valid_sources[0x3b]	2460	1			T5	1		T43	1		T16	3
valid_sources[0x3c]	1805	1			T4	1		T5	1		T43	1
valid_sources[0x3d]	1489	1			T5	1		T16	4		T32	5
valid_sources[0x3e]	2347	1			T1	1		T5	2		T43	4
valid_sources[0x3f]	1535	1			T32	29		T18	6		T28	4
valid_sources[0x40]	1542	1			T5	1		T43	1		T16	4
valid_sources[0x41]	3664	1			T1	1		T43	2		T21	2
valid_sources[0x42]	1496	1			T4	3		T16	3		T32	3
valid_sources[0x43]	1513	1			T2	1		T35	1		T17	1
valid_sources[0x44]	1387	1			T4	1		T18	4		T28	3
valid_sources[0x45]	1463	1			T1	1		T5	1		T16	6
valid_sources[0x46]	1778	1			T43	1		T16	22		T32	4
valid_sources[0x47]	1663	1			T1	1		T35	1		T18	11
valid_sources[0x48]	1553	1			T1	1		T5	1		T16	18
valid_sources[0x49]	1680	1			T43	3		T32	13		T35	1
valid_sources[0x4a]	1533	1			T6	11		T32	1		T18	8
valid_sources[0x4b]	2321	1			T2	1		T5	1		T32	16
valid_sources[0x4c]	1546	1			T1	1		T5	1		T43	2
valid_sources[0x4d]	1517	1			T2	1		T5	1		T43	1
valid_sources[0x4e]	1747	1			T1	1		T37	3		T18	4
valid_sources[0x4f]	1579	1			T1	1		T5	1		T43	1
valid_sources[0x50]	3515	1			T2	1		T5	2		T6	1
valid_sources[0x51]	1654	1			T1	2		T43	3		T32	1
valid_sources[0x52]	1480	1			T16	7		T34	1		T18	4
valid_sources[0x53]	2996	1			T16	9		T17	1		T38	2
valid_sources[0x54]	1566	1			T5	2		T43	1		T16	12
valid_sources[0x55]	1740	1			T1	1		T4	1		T5	2
valid_sources[0x56]	1726	1			T2	2		T4	2		T32	2
valid_sources[0x57]	2010	1			T1	3		T5	2		T6	2
valid_sources[0x58]	1554	1			T1	1		T2	1		T43	1
valid_sources[0x59]	3470	1			T1	2		T43	1		T32	3
valid_sources[0x5a]	2169	1			T35	2		T18	4		T28	1
valid_sources[0x5b]	2530	1			T4	2		T6	4		T16	7
valid_sources[0x5c]	3316	1			T1	1		T5	1		T16	28
valid_sources[0x5d]	1659	1			T5	2		T32	5		T37	1
valid_sources[0x5e]	1537	1			T5	1		T16	2		T32	3
valid_sources[0x5f]	1772	1			T1	1		T43	7		T34	1
valid_sources[0x60]	1998	1			T2	2		T6	6		T43	2
valid_sources[0x61]	1494	1			T5	1		T43	5		T32	4
valid_sources[0x62]	2163	1			T43	4		T16	12		T21	2
valid_sources[0x63]	3998	1			T14	12		T43	1		T16	3
valid_sources[0x64]	1534	1			T2	1		T4	2		T5	1
valid_sources[0x65]	1339	1			T1	1		T4	4		T43	3
valid_sources[0x66]	1575	1			T5	1		T43	2		T32	6
valid_sources[0x67]	2572	1			T1	1		T43	2		T16	37
valid_sources[0x68]	1281	1			T4	1		T5	1		T43	3
valid_sources[0x69]	1828	1			T4	2		T5	1		T43	2
valid_sources[0x6a]	1726	1			T2	1		T43	2		T34	2
valid_sources[0x6b]	1637	1			T4	2		T5	2		T32	7
valid_sources[0x6c]	2758	1			T1	1		T43	4		T32	2
valid_sources[0x6d]	1817	1			T17	2		T18	3		T28	5
valid_sources[0x6e]	1468	1			T5	3		T14	21		T43	1
valid_sources[0x6f]	1450	1			T1	1		T2	1		T5	2
valid_sources[0x70]	1353	1			T5	2		T35	2		T28	1
valid_sources[0x71]	3864	1			T1	2		T5	1		T43	2
valid_sources[0x72]	1948	1			T2	1		T6	2		T43	3
valid_sources[0x73]	2081	1			T35	1		T18	1		T60	3
valid_sources[0x74]	1395	1			T4	2		T6	3		T43	7
valid_sources[0x75]	1784	1			T1	2		T5	1		T16	1
valid_sources[0x76]	1370	1			T1	1		T5	1		T43	2
valid_sources[0x77]	1609	1			T5	3		T43	1		T34	1
valid_sources[0x78]	1661	1			T1	3		T5	1		T43	2
valid_sources[0x79]	1942	1			T35	2		T37	2		T38	2
valid_sources[0x7a]	1658	1			T5	1		T6	10		T43	2
valid_sources[0x7b]	1575	1			T38	1		T18	5		T28	5
valid_sources[0x7c]	2025	1			T5	1		T16	17		T32	10
valid_sources[0x7d]	1622	1			T14	5		T16	20		T32	32
valid_sources[0x7e]	2018	1			T1	1		T5	1		T35	3
valid_sources[0x7f]	2295	1			T5	1		T43	2		T37	1
valid_sources[0x80]	1729	1			T1	2		T6	15		T43	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

73357

1

T1

44

T2

13

T3

9

values[0x0]

all_enables

biggest_size

44573

1

T1

8

T2

2

T3

7

values[0x1]

all_enables

biggest_size

25371

1

T1

1

T2

1

T3

1