Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	15813849	14965	0	0
intr_enable_rd_A	15813849	18362	0	0
reset_en_rd_A	15813849	1528	0	0
reset_en_regwen_rd_A	15813849	1120	0	0
wake_info_capture_dis_rd_A	15813849	1321	0	0
wakeup_en_rd_A	15813849	2410	0	0
wakeup_en_regwen_rd_A	15813849	1305	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15813849	14965	0	0
T19	888	0	0	0
T22	20588	0	0	0
T24	73177	84	0	0
T25	0	3	0	0
T26	0	5	0	0
T51	0	174	0	0
T52	0	81	0	0
T77	11872	0	0	0
T78	0	29	0	0
T131	33969	0	0	0
T134	0	4	0	0
T135	0	39	0	0
T136	0	12	0	0
T137	0	14	0	0
T138	52979	0	0	0
T139	1283	0	0	0
T140	2761	0	0	0
T141	7271	0	0	0
T142	10504	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15813849	18362	0	0
T5	2454	40	0	0
T6	10086	0	0	0
T7	7016	0	0	0
T8	1336	0	0	0
T9	1392	0	0	0
T10	936	0	0	0
T11	9498	0	0	0
T14	2395	0	0	0
T15	4192	0	0	0
T17	0	47	0	0
T27	0	28	0	0
T36	0	12	0	0
T38	0	48	0	0
T41	1466	0	0	0
T42	0	83	0	0
T43	0	58	0	0
T141	0	109	0	0
T143	0	75	0	0
T144	0	6	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15813849	1528	0	0
T49	0	38	0	0
T69	0	105	0	0
T71	0	19	0	0
T134	59883	11	0	0
T145	0	29	0	0
T146	0	10	0	0
T147	0	25	0	0
T148	0	11	0	0
T149	0	21	0	0
T150	0	18	0	0
T151	1528	0	0	0
T152	872	0	0	0
T153	10521	0	0	0
T154	3369	0	0	0
T155	1339	0	0	0
T156	953	0	0	0
T157	1617	0	0	0
T158	2434	0	0	0
T159	3856	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15813849	1120	0	0
T49	0	27	0	0
T71	0	8	0	0
T134	59883	15	0	0
T136	0	5	0	0
T145	0	14	0	0
T146	0	13	0	0
T147	0	17	0	0
T148	0	5	0	0
T149	0	6	0	0
T150	0	14	0	0
T151	1528	0	0	0
T152	872	0	0	0
T153	10521	0	0	0
T154	3369	0	0	0
T155	1339	0	0	0
T156	953	0	0	0
T157	1617	0	0	0
T158	2434	0	0	0
T159	3856	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15813849	1321	0	0
T49	0	11	0	0
T71	0	14	0	0
T134	59883	8	0	0
T136	0	4	0	0
T145	0	8	0	0
T146	0	20	0	0
T147	0	14	0	0
T148	0	15	0	0
T149	0	9	0	0
T150	0	17	0	0
T151	1528	0	0	0
T152	872	0	0	0
T153	10521	0	0	0
T154	3369	0	0	0
T155	1339	0	0	0
T156	953	0	0	0
T157	1617	0	0	0
T158	2434	0	0	0
T159	3856	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15813849	2410	0	0
T49	0	86	0	0
T71	0	4	0	0
T134	59883	7	0	0
T136	0	4	0	0
T145	0	23	0	0
T146	0	9	0	0
T147	0	24	0	0
T148	0	10	0	0
T149	0	19	0	0
T150	0	12	0	0
T151	1528	0	0	0
T152	872	0	0	0
T153	10521	0	0	0
T154	3369	0	0	0
T155	1339	0	0	0
T156	953	0	0	0
T157	1617	0	0	0
T158	2434	0	0	0
T159	3856	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15813849	1305	0	0
T49	0	34	0	0
T55	0	12	0	0
T71	0	12	0	0
T134	59883	14	0	0
T145	0	23	0	0
T146	0	25	0	0
T147	0	18	0	0
T148	0	12	0	0
T149	0	11	0	0
T150	0	13	0	0
T151	1528	0	0	0
T152	872	0	0	0
T153	10521	0	0	0
T154	3369	0	0	0
T155	1339	0	0	0
T156	953	0	0	0
T157	1617	0	0	0
T158	2434	0	0	0
T159	3856	0	0	0