Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	45715083	95851	0	0
StatusRise_A	45715083	107764	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	45715083	95851	0	0
T1	11859	7	0	0
T2	3618	6	0	0
T3	7056	36	0	0
T4	10884	33	0	0
T5	7362	35	0	0
T6	30258	54	0	0
T7	21048	84	0	0
T8	4008	6	0	0
T9	4176	0	0	0
T10	2808	0	0	0
T11	0	9	0	0
T14	0	54	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	45715083	107764	0	0
T1	11859	9	0	0
T2	3618	9	0	0
T3	7056	39	0	0
T4	10884	36	0	0
T5	7362	37	0	0
T6	30258	56	0	0
T7	21048	89	0	0
T8	4008	9	0	0
T9	4176	9	0	0
T10	2808	21	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	15238361	35760	0	0
StatusRise_A	15238361	40023	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15238361	35760	0	0
T1	3953	3	0	0
T2	1206	2	0	0
T3	2352	12	0	0
T4	3628	13	0	0
T5	2454	13	0	0
T6	10086	20	0	0
T7	7016	35	0	0
T8	1336	2	0	0
T9	1392	0	0	0
T10	936	0	0	0
T11	0	3	0	0
T14	0	18	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15238361	40023	0	0
T1	3953	4	0	0
T2	1206	3	0	0
T3	2352	13	0	0
T4	3628	14	0	0
T5	2454	14	0	0
T6	10086	21	0	0
T7	7016	37	0	0
T8	1336	3	0	0
T9	1392	3	0	0
T10	936	7	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	15238361	35760	0	0
StatusRise_A	15238361	40023	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15238361	35760	0	0
T1	3953	3	0	0
T2	1206	2	0	0
T3	2352	12	0	0
T4	3628	13	0	0
T5	2454	13	0	0
T6	10086	20	0	0
T7	7016	35	0	0
T8	1336	2	0	0
T9	1392	0	0	0
T10	936	0	0	0
T11	0	3	0	0
T14	0	18	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15238361	40023	0	0
T1	3953	4	0	0
T2	1206	3	0	0
T3	2352	13	0	0
T4	3628	14	0	0
T5	2454	14	0	0
T6	10086	21	0	0
T7	7016	37	0	0
T8	1336	3	0	0
T9	1392	3	0	0
T10	936	7	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	15238361	24331	0	0
StatusRise_A	15238361	27718	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15238361	24331	0	0
T1	3953	1	0	0
T2	1206	2	0	0
T3	2352	12	0	0
T4	3628	7	0	0
T5	2454	9	0	0
T6	10086	14	0	0
T7	7016	14	0	0
T8	1336	2	0	0
T9	1392	0	0	0
T10	936	0	0	0
T11	0	3	0	0
T14	0	18	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15238361	27718	0	0
T1	3953	1	0	0
T2	1206	3	0	0
T3	2352	13	0	0
T4	3628	8	0	0
T5	2454	9	0	0
T6	10086	14	0	0
T7	7016	15	0	0
T8	1336	3	0	0
T9	1392	3	0	0
T10	936	7	0	0