Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

41                      
42         1/1            always_comb reset_or_disable = !rst_ni || disable_sva;
           Tests:       T1 T2 T3 
43         1/1            always_comb esc_reset_or_disable = !rst_esc_ni || disable_sva;
           Tests:       T1 T2 T3 
44         1/1            always_comb slow_reset_or_disable = !rst_slow_ni || disable_sva;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	15238945	11689	0	0
EscTimeoutStoppedByClReset_A	15238361	2140701	0	0
EscTimeoutTriggersReset_A	3356610	427	0	0
RomAllowActiveState_A	15238361	39638	0	0
RomAllowCheckGoodState_A	15238361	39689	0	0
RomBlockActiveState_A	15238361	30102	0	0
RomBlockCheckGoodState_A	15238361	357253	0	0
RomIntgChkDisFalse_A	15238361	14692843	0	0
RomIntgChkDisTrue_A	15238361	165616	0	0
RstreqChkEsctimeout_A	15238361	2950	0	0
RstreqChkFsmterm_A	15238361	140	0	0
RstreqChkGlbesc_A	15238361	2950	0	0
RstreqChkMainpd_A	15238361	681211	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15238945	11689	0	0
T11	9499	87	0	0
T12	1258	0	0	0
T13	0	5	0	0
T15	4192	0	0	0
T16	25652	0	0	0
T21	24849	0	0	0
T31	2239	0	0	0
T32	56432	0	0	0
T39	0	176	0	0
T41	1467	0	0	0
T42	7024	0	0	0
T43	10862	0	0	0
T95	0	105	0	0
T139	0	6	0	0
T142	0	309	0	0
T153	0	365	0	0
T160	0	279	0	0
T161	0	18	0	0
T162	0	324	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15238361	2140701	0	0
T1	3953	24	0	0
T2	1206	22	0	0
T3	2352	196	0	0
T4	3628	558	0	0
T5	2454	0	0	0
T6	10086	1607	0	0
T7	7016	1068	0	0
T8	1336	43	0	0
T9	1392	14	0	0
T10	936	44	0	0
T14	0	246	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3356610	427	0	0
T11	348	4	0	0
T12	222	4	0	0
T13	0	4	0	0
T15	311	0	0	0
T16	5219	0	0	0
T21	2487	0	0	0
T31	398	0	0	0
T32	5553	0	0	0
T39	0	5	0	0
T41	509	0	0	0
T42	514	0	0	0
T43	2487	0	0	0
T95	0	6	0	0
T139	0	3	0	0
T142	0	4	0	0
T160	0	4	0	0
T163	0	2	0	0
T164	0	4	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15238361	39638	0	0
T1	3953	4	0	0
T2	1206	3	0	0
T3	2352	13	0	0
T4	3628	14	0	0
T5	2454	14	0	0
T6	10086	21	0	0
T7	7016	37	0	0
T8	1336	3	0	0
T9	1392	3	0	0
T10	936	7	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15238361	39689	0	0
T1	3953	4	0	0
T2	1206	3	0	0
T3	2352	13	0	0
T4	3628	14	0	0
T5	2454	14	0	0
T6	10086	21	0	0
T7	7016	37	0	0
T8	1336	3	0	0
T9	1392	3	0	0
T10	936	7	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15238361	30102	0	0
T12	1258	0	0	0
T15	4192	613	0	0
T16	25652	0	0	0
T21	24848	0	0	0
T27	0	610	0	0
T31	2238	0	0	0
T32	56431	0	0	0
T33	1260	0	0	0
T41	1466	0	0	0
T42	7023	0	0	0
T43	10862	0	0	0
T47	0	1554	0	0
T82	0	6	0	0
T84	0	1	0	0
T97	0	2	0	0
T98	0	530	0	0
T152	0	21	0	0
T165	0	218	0	0
T166	0	359	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15238361	357253	0	0
T7	7016	459	0	0
T8	1336	0	0	0
T9	1392	0	0	0
T10	936	0	0	0
T11	9498	0	0	0
T14	2395	0	0	0
T15	4192	1041	0	0
T16	0	2272	0	0
T18	0	184	0	0
T24	0	46	0	0
T27	0	861	0	0
T28	0	4090	0	0
T32	0	4078	0	0
T34	0	46	0	0
T41	1466	0	0	0
T42	7023	0	0	0
T43	10862	0	0	0
T76	0	227	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15238361	14692843	0	0
T1	3953	3894	0	0
T2	1206	1143	0	0
T3	2352	2285	0	0
T4	3628	3545	0	0
T5	2454	2373	0	0
T6	10086	9994	0	0
T7	7016	6908	0	0
T8	1336	1282	0	0
T9	1392	1165	0	0
T10	936	435	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15238361	165616	0	0
T12	1258	0	0	0
T16	25652	1084	0	0
T21	24848	0	0	0
T27	0	463	0	0
T28	0	567	0	0
T31	2238	0	0	0
T32	56431	0	0	0
T33	1260	0	0	0
T34	1288	0	0	0
T35	3755	0	0	0
T36	3584	0	0	0
T37	4504	0	0	0
T47	0	2096	0	0
T97	0	215	0	0
T98	0	1343	0	0
T166	0	197	0	0
T167	0	1214	0	0
T168	0	527	0	0
T169	0	1088	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15238361	2950	0	0
T3	2352	6	0	0
T4	3628	0	0	0
T5	2454	0	0	0
T6	10086	0	0	0
T7	7016	0	0	0
T8	1336	0	0	0
T9	1392	2	0	0
T10	936	0	0	0
T11	9498	2	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	2395	8	0	0
T15	0	4	0	0
T18	0	10	0	0
T21	0	10	0	0
T36	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15238361	140	0	0
T17	4497	0	0	0
T21	24848	20	0	0
T22	0	20	0	0
T23	0	20	0	0
T29	0	40	0	0
T30	0	40	0	0
T31	2238	0	0	0
T32	56431	0	0	0
T33	1260	0	0	0
T34	1288	0	0	0
T35	3755	0	0	0
T36	3584	0	0	0
T37	4504	0	0	0
T38	8252	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15238361	2950	0	0
T3	2352	6	0	0
T4	3628	0	0	0
T5	2454	0	0	0
T6	10086	0	0	0
T7	7016	0	0	0
T8	1336	0	0	0
T9	1392	2	0	0
T10	936	0	0	0
T11	9498	2	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	2395	8	0	0
T15	0	4	0	0
T18	0	10	0	0
T21	0	10	0	0
T36	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15238361	681211	0	0
T3	2352	96	0	0
T4	3628	0	0	0
T5	2454	0	0	0
T6	10086	0	0	0
T7	7016	308	0	0
T8	1336	0	0	0
T9	1392	0	0	0
T10	936	27	0	0
T11	9498	0	0	0
T14	2395	78	0	0
T15	0	85	0	0
T16	0	2521	0	0
T18	0	548	0	0
T32	0	5729	0	0
T34	0	123	0	0
T36	0	300	0	0