Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_wakeup_intr_cg_wrap::wakeup_intr_cg

Group : pwrmgr_env_pkg::pwrmgr_wakeup_intr_cg_wrap::wakeup_intr_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

6 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
WakeupAonTimer_intr_cg	100.00	1	100	1	64	64
WakeupDbgCable_intr_cg	100.00	1	100	1	64	64
WakeupPin_intr_cg	100.00	1	100	1	64	64
WakeupSensorCtrl_intr_cg	100.00	1	100	1	64	64
WakeupSysrst_intr_cg	100.00	1	100	1	64	64
WakeupUsb_intr_cg	100.00	1	100	1	64	64

---

Group Instance : WakeupAonTimer_intr_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupAonTimer_intr_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupAonTimer_intr_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
interrupt_cp	2	0	2	100.00	100	1	1	2
status_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupAonTimer_intr_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
interrupt_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupDbgCable_intr_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupDbgCable_intr_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupDbgCable_intr_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
interrupt_cp	2	0	2	100.00	100	1	1	2
status_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupDbgCable_intr_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
interrupt_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupPin_intr_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupPin_intr_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupPin_intr_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
interrupt_cp	2	0	2	100.00	100	1	1	2
status_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupPin_intr_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
interrupt_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupSensorCtrl_intr_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupSensorCtrl_intr_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupSensorCtrl_intr_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
interrupt_cp	2	0	2	100.00	100	1	1	2
status_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupSensorCtrl_intr_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
interrupt_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupSysrst_intr_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupSysrst_intr_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupSysrst_intr_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
interrupt_cp	2	0	2	100.00	100	1	1	2
status_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupSysrst_intr_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
interrupt_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupUsb_intr_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupUsb_intr_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupUsb_intr_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
interrupt_cp	2	0	2	100.00	100	1	1	2
status_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupUsb_intr_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
interrupt_cross	8	0	8	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36203

1

T1

2

T2

2

T3

7

auto[1]

9366

1

T1

1

T3

2

T6

6

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34529

1

T1

2

T2

2

T3

4

auto[1]

11040

1

T1

1

T3

5

T6

7

---

Summary for Variable status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for status_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25388

1

T1

1

T2

2

T3

4

auto[1]

20181

1

T1

2

T3

5

T4

13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19194

1

T1

2

T2

1

T3

1

auto[1]

26375

1

T1

1

T2

1

T3

8

---

Summary for Cross interrupt_cross

Samples crossed: enable_cp status_cp wakeup_cp interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for interrupt_cross

Bins

enable_cp

status_cp

wakeup_cp

interrupt_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

11771

1

T1

1

T2

1

T3

1

auto[0]

auto[0]

auto[1]

auto[0]

9100

1

T2

1

T3

3

T5

8

auto[0]

auto[1]

auto[0]

auto[0]

5757

1

T1

1

T4

13

T6

4

auto[0]

auto[1]

auto[1]

auto[0]

2524

1

T5

5

T16

6

T17

2

auto[1]

auto[0]

auto[0]

auto[0]

806

1

T6

2

T33

4

T36

4

auto[1]

auto[0]

auto[1]

auto[0]

3711

1

T10

1

T14

10

T15

8

auto[1]

auto[1]

auto[0]

auto[0]

860

1

T6

2

T14

6

T15

6

auto[1]

auto[1]

auto[1]

auto[1]

3989

1

T1

1

T3

2

T6

2

User Defined Cross Bins for interrupt_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
no_wakeup	0	Excluded
disable_pin	0	Excluded
no_status_pin	0	Excluded
missing_int	0	Excluded

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36311

1

T1

3

T2

1

T3

8

auto[1]

9258

1

T2

1

T3

1

T6

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34529

1

T1

2

T2

2

T3

4

auto[1]

11040

1

T1

1

T3

5

T6

7

---

Summary for Variable status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for status_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25388

1

T1

1

T2

2

T3

4

auto[1]

20181

1

T1

2

T3

5

T4

13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19194

1

T1

2

T2

1

T3

1

auto[1]

26375

1

T1

1

T2

1

T3

8

---

Summary for Cross interrupt_cross

Samples crossed: enable_cp status_cp wakeup_cp interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for interrupt_cross

Bins

enable_cp

status_cp

wakeup_cp

interrupt_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

11743

1

T1

1

T2

1

T3

1

auto[0]

auto[0]

auto[1]

auto[0]

9243

1

T3

3

T5

8

T6

6

auto[0]

auto[1]

auto[0]

auto[0]

5731

1

T1

1

T4

13

T6

2

auto[0]

auto[1]

auto[1]

auto[0]

2524

1

T5

5

T16

6

T17

2

auto[1]

auto[0]

auto[0]

auto[0]

834

1

T6

6

T14

2

T15

4

auto[1]

auto[0]

auto[1]

auto[0]

3568

1

T2

1

T10

3

T14

7

auto[1]

auto[1]

auto[0]

auto[0]

886

1

T6

4

T14

4

T15

6

auto[1]

auto[1]

auto[1]

auto[1]

3970

1

T3

1

T6

2

T14

6

User Defined Cross Bins for interrupt_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
no_wakeup	0	Excluded
disable_pin	0	Excluded
no_status_pin	0	Excluded
missing_int	0	Excluded

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36338

1

T1

2

T2

1

T3

7

auto[1]

9231

1

T1

1

T2

1

T3

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34529

1

T1

2

T2

2

T3

4

auto[1]

11040

1

T1

1

T3

5

T6

7

---

Summary for Variable status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for status_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25388

1

T1

1

T2

2

T3

4

auto[1]

20181

1

T1

2

T3

5

T4

13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19194

1

T1

2

T2

1

T3

1

auto[1]

26375

1

T1

1

T2

1

T3

8

---

Summary for Cross interrupt_cross

Samples crossed: enable_cp status_cp wakeup_cp interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for interrupt_cross

Bins

enable_cp

status_cp

wakeup_cp

interrupt_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

11763

1

T1

1

T2

1

T3

1

auto[0]

auto[0]

auto[1]

auto[0]

9157

1

T3

2

T5

8

T6

4

auto[0]

auto[1]

auto[0]

auto[0]

5747

1

T1

1

T4

13

T6

4

auto[0]

auto[1]

auto[1]

auto[0]

2524

1

T5

5

T16

6

T17

2

auto[1]

auto[0]

auto[0]

auto[0]

814

1

T14

4

T15

2

T36

2

auto[1]

auto[0]

auto[1]

auto[0]

3654

1

T2

1

T3

1

T6

2

auto[1]

auto[1]

auto[0]

auto[0]

870

1

T6

2

T14

4

T15

6

auto[1]

auto[1]

auto[1]

auto[1]

3893

1

T1

1

T3

1

T6

4

User Defined Cross Bins for interrupt_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
no_wakeup	0	Excluded
disable_pin	0	Excluded
no_status_pin	0	Excluded
missing_int	0	Excluded

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36202

1

T1

3

T2

2

T3

7

auto[1]

9367

1

T3

2

T6

3

T10

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34529

1

T1

2

T2

2

T3

4

auto[1]

11040

1

T1

1

T3

5

T6

7

---

Summary for Variable status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for status_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25388

1

T1

1

T2

2

T3

4

auto[1]

20181

1

T1

2

T3

5

T4

13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19194

1

T1

2

T2

1

T3

1

auto[1]

26375

1

T1

1

T2

1

T3

8

---

Summary for Cross interrupt_cross

Samples crossed: enable_cp status_cp wakeup_cp interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for interrupt_cross

Bins

enable_cp

status_cp

wakeup_cp

interrupt_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

11747

1

T1

1

T2

1

T3

1

auto[0]

auto[0]

auto[1]

auto[0]

9213

1

T2

1

T3

1

T5

8

auto[0]

auto[1]

auto[0]

auto[0]

5725

1

T1

1

T4

13

T6

4

auto[0]

auto[1]

auto[1]

auto[0]

2524

1

T5

5

T16

6

T17

2

auto[1]

auto[0]

auto[0]

auto[0]

830

1

T15

6

T27

8

T97

2

auto[1]

auto[0]

auto[1]

auto[0]

3598

1

T3

2

T10

4

T14

10

auto[1]

auto[1]

auto[0]

auto[0]

892

1

T6

2

T14

2

T15

10

auto[1]

auto[1]

auto[1]

auto[1]

4047

1

T6

1

T10

1

T14

11

User Defined Cross Bins for interrupt_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
no_wakeup	0	Excluded
disable_pin	0	Excluded
no_status_pin	0	Excluded
missing_int	0	Excluded

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36304

1

T1

2

T2

2

T3

8

auto[1]

9265

1

T1

1

T3

1

T6

7

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34529

1

T1

2

T2

2

T3

4

auto[1]

11040

1

T1

1

T3

5

T6

7

---

Summary for Variable status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for status_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25388

1

T1

1

T2

2

T3

4

auto[1]

20181

1

T1

2

T3

5

T4

13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19194

1

T1

2

T2

1

T3

1

auto[1]

26375

1

T1

1

T2

1

T3

8

---

Summary for Cross interrupt_cross

Samples crossed: enable_cp status_cp wakeup_cp interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for interrupt_cross

Bins

enable_cp

status_cp

wakeup_cp

interrupt_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

11686

1

T1

1

T2

1

T3

1

auto[0]

auto[0]

auto[1]

auto[0]

9169

1

T2

1

T3

3

T5

8

auto[0]

auto[1]

auto[0]

auto[0]

5789

1

T1

1

T4

13

T6

6

auto[0]

auto[1]

auto[1]

auto[0]

2524

1

T5

5

T16

6

T17

2

auto[1]

auto[0]

auto[0]

auto[0]

891

1

T14

4

T33

2

T36

8

auto[1]

auto[0]

auto[1]

auto[0]

3642

1

T6

5

T10

2

T14

10

auto[1]

auto[1]

auto[0]

auto[0]

828

1

T14

8

T15

10

T33

4

auto[1]

auto[1]

auto[1]

auto[1]

3904

1

T1

1

T3

1

T6

2

User Defined Cross Bins for interrupt_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
no_wakeup	0	Excluded
disable_pin	0	Excluded
no_status_pin	0	Excluded
missing_int	0	Excluded

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36199

1

T1

3

T2

2

T3

8

auto[1]

9370

1

T3

1

T6

10

T10

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34529

1

T1

2

T2

2

T3

4

auto[1]

11040

1

T1

1

T3

5

T6

7

---

Summary for Variable status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for status_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25388

1

T1

1

T2

2

T3

4

auto[1]

20181

1

T1

2

T3

5

T4

13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19194

1

T1

2

T2

1

T3

1

auto[1]

26375

1

T1

1

T2

1

T3

8

---

Summary for Cross interrupt_cross

Samples crossed: enable_cp status_cp wakeup_cp interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for interrupt_cross

Bins

enable_cp

status_cp

wakeup_cp

interrupt_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

11713

1

T1

1

T2

1

T3

1

auto[0]

auto[0]

auto[1]

auto[0]

9235

1

T2

1

T3

3

T5

8

auto[0]

auto[1]

auto[0]

auto[0]

5733

1

T1

1

T4

13

T6

2

auto[0]

auto[1]

auto[1]

auto[0]

2524

1

T5

5

T16

6

T17

2

auto[1]

auto[0]

auto[0]

auto[0]

864

1

T14

2

T15

2

T33

2

auto[1]

auto[0]

auto[1]

auto[0]

3576

1

T6

3

T10

1

T14

2

auto[1]

auto[1]

auto[0]

auto[0]

884

1

T6

4

T14

8

T15

10

auto[1]

auto[1]

auto[1]

auto[1]

4046

1

T3

1

T6

3

T10

2

User Defined Cross Bins for interrupt_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
no_wakeup	0	Excluded
disable_pin	0	Excluded
no_status_pin	0	Excluded
missing_int	0	Excluded