Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	388672	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

152233

1

T1

10

T2

3

T3

30

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	280668	1			T1	21		T2	11		T3	51
values[0x0]	129980	1			T1	5		T2	5		T3	25
values[0x1]	130257	1			T1	5		T2	3		T3	33

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	308095	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

232810

1

T1

14

T2

6

T3

49

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1496	1			T5	1		T8	1		T15	5
valid_sources[0x01]	1949	1			T8	2		T14	2		T15	4
valid_sources[0x02]	2205	1			T6	1		T8	1		T15	3
valid_sources[0x03]	1649	1			T3	1		T5	2		T14	2
valid_sources[0x04]	1631	1			T5	1		T6	1		T14	7
valid_sources[0x05]	1842	1			T4	2		T6	1		T8	1
valid_sources[0x06]	2428	1			T6	2		T15	2		T34	1
valid_sources[0x07]	1782	1			T3	1		T6	1		T8	1
valid_sources[0x08]	2554	1			T3	1		T8	1		T15	4
valid_sources[0x09]	1859	1			T4	1		T5	2		T6	1
valid_sources[0x0a]	1600	1			T2	1		T3	2		T4	3
valid_sources[0x0b]	1475	1			T3	2		T5	1		T14	4
valid_sources[0x0c]	2105	1			T5	4		T8	1		T15	3
valid_sources[0x0d]	1764	1			T5	1		T6	2		T8	1
valid_sources[0x0e]	2405	1			T8	2		T15	1		T16	1
valid_sources[0x0f]	2095	1			T6	1		T8	2		T14	12
valid_sources[0x10]	1672	1			T3	2		T4	1		T6	3
valid_sources[0x11]	2621	1			T6	3		T8	1		T14	5
valid_sources[0x12]	1818	1			T3	1		T4	1		T6	2
valid_sources[0x13]	2453	1			T3	1		T4	3		T5	1
valid_sources[0x14]	1908	1			T3	1		T4	2		T5	1
valid_sources[0x15]	1555	1			T5	2		T6	1		T8	1
valid_sources[0x16]	3968	1			T3	1		T5	2		T8	1
valid_sources[0x17]	1529	1			T4	2		T6	1		T15	4
valid_sources[0x18]	1617	1			T15	2		T78	1		T34	2
valid_sources[0x19]	1707	1			T3	1		T6	1		T15	5
valid_sources[0x1a]	1951	1			T3	1		T4	1		T6	1
valid_sources[0x1b]	3270	1			T4	4		T6	1		T8	2
valid_sources[0x1c]	1650	1			T4	1		T6	1		T8	2
valid_sources[0x1d]	1819	1			T3	2		T4	1		T6	2
valid_sources[0x1e]	1537	1			T3	3		T4	1		T6	1
valid_sources[0x1f]	3082	1			T3	2		T6	1		T8	2
valid_sources[0x20]	1947	1			T2	2		T4	1		T8	2
valid_sources[0x21]	1848	1			T3	2		T4	1		T6	1
valid_sources[0x22]	1686	1			T4	2		T5	2		T8	1
valid_sources[0x23]	1867	1			T2	1		T5	2		T8	1
valid_sources[0x24]	1563	1			T3	1		T4	1		T8	2
valid_sources[0x25]	2065	1			T4	2		T5	2		T8	1
valid_sources[0x26]	1563	1			T5	1		T6	1		T14	3
valid_sources[0x27]	1687	1			T4	4		T5	2		T6	2
valid_sources[0x28]	1557	1			T2	2		T5	1		T8	1
valid_sources[0x29]	2240	1			T4	4		T15	3		T36	1
valid_sources[0x2a]	1808	1			T4	3		T5	1		T6	1
valid_sources[0x2b]	2550	1			T6	1		T15	3		T16	3
valid_sources[0x2c]	2609	1			T4	1		T5	4		T14	10
valid_sources[0x2d]	1566	1			T4	1		T6	1		T14	13
valid_sources[0x2e]	1730	1			T4	1		T6	1		T14	1
valid_sources[0x2f]	1820	1			T5	4		T6	1		T14	5
valid_sources[0x30]	2405	1			T4	6		T6	4		T14	4
valid_sources[0x31]	4220	1			T8	1		T15	3		T78	1
valid_sources[0x32]	1491	1			T6	2		T8	1		T34	1
valid_sources[0x33]	1803	1			T4	4		T5	1		T6	2
valid_sources[0x34]	1639	1			T4	1		T6	2		T15	3
valid_sources[0x35]	2231	1			T5	3		T8	1		T14	6
valid_sources[0x36]	1753	1			T5	3		T14	2		T15	7
valid_sources[0x37]	1485	1			T3	2		T4	3		T6	1
valid_sources[0x38]	2427	1			T2	1		T3	1		T5	1
valid_sources[0x39]	1912	1			T8	2		T14	4		T15	1
valid_sources[0x3a]	1577	1			T4	3		T5	1		T6	1
valid_sources[0x3b]	2072	1			T5	2		T6	1		T36	13
valid_sources[0x3c]	2542	1			T4	1		T6	2		T8	1
valid_sources[0x3d]	1954	1			T6	1		T8	1		T14	1
valid_sources[0x3e]	1611	1			T3	1		T4	2		T6	1
valid_sources[0x3f]	1709	1			T4	1		T14	6		T15	5
valid_sources[0x40]	1881	1			T4	1		T6	2		T15	4
valid_sources[0x41]	2082	1			T3	1		T8	1		T15	1
valid_sources[0x42]	1590	1			T5	1		T14	3		T15	2
valid_sources[0x43]	1708	1			T5	2		T6	1		T8	1
valid_sources[0x44]	2262	1			T4	3		T5	2		T6	1
valid_sources[0x45]	2623	1			T5	1		T8	2		T15	1
valid_sources[0x46]	1504	1			T4	3		T8	2		T14	4
valid_sources[0x47]	1850	1			T2	1		T6	4		T8	3
valid_sources[0x48]	1670	1			T3	1		T5	1		T6	1
valid_sources[0x49]	3525	1			T4	4		T6	1		T8	2
valid_sources[0x4a]	1569	1			T3	2		T8	2		T14	25
valid_sources[0x4b]	3048	1			T5	2		T6	1		T8	2
valid_sources[0x4c]	2517	1			T3	1		T8	3		T14	7
valid_sources[0x4d]	1786	1			T5	2		T6	3		T14	3
valid_sources[0x4e]	1601	1			T3	1		T4	1		T8	1
valid_sources[0x4f]	1625	1			T4	2		T8	1		T15	4
valid_sources[0x50]	1503	1			T6	1		T14	1		T15	1
valid_sources[0x51]	1718	1			T2	1		T4	1		T5	1
valid_sources[0x52]	1573	1			T6	3		T8	1		T15	7
valid_sources[0x53]	1615	1			T4	1		T6	1		T8	2
valid_sources[0x54]	1805	1			T4	3		T5	2		T8	1
valid_sources[0x55]	2341	1			T8	2		T14	5		T15	9
valid_sources[0x56]	3131	1			T3	1		T6	2		T8	1
valid_sources[0x57]	2775	1			T8	1		T14	10		T15	1
valid_sources[0x58]	3256	1			T3	1		T4	2		T6	5
valid_sources[0x59]	1437	1			T5	1		T8	2		T14	4
valid_sources[0x5a]	3079	1			T3	1		T5	1		T8	1
valid_sources[0x5b]	3099	1			T3	2		T14	6		T15	4
valid_sources[0x5c]	2634	1			T4	2		T5	1		T6	1
valid_sources[0x5d]	1892	1			T8	2		T14	2		T15	8
valid_sources[0x5e]	1610	1			T3	1		T6	1		T8	1
valid_sources[0x5f]	1612	1			T4	1		T8	1		T15	1
valid_sources[0x60]	2378	1			T14	2		T15	3		T16	5
valid_sources[0x61]	3689	1			T3	1		T4	1		T6	2
valid_sources[0x62]	2727	1			T4	1		T6	1		T15	2
valid_sources[0x63]	1730	1			T15	1		T16	3		T17	1
valid_sources[0x64]	2500	1			T6	3		T8	1		T15	3
valid_sources[0x65]	1946	1			T3	1		T6	1		T14	2
valid_sources[0x66]	2790	1			T5	1		T6	1		T8	1
valid_sources[0x67]	1835	1			T5	2		T6	1		T8	1
valid_sources[0x68]	1868	1			T3	1		T5	2		T8	2
valid_sources[0x69]	1826	1			T5	1		T8	1		T14	8
valid_sources[0x6a]	2565	1			T4	2		T15	2		T16	13
valid_sources[0x6b]	1487	1			T3	1		T4	2		T8	2
valid_sources[0x6c]	2644	1			T6	1		T8	1		T14	2
valid_sources[0x6d]	1777	1			T6	2		T8	2		T14	14
valid_sources[0x6e]	1724	1			T4	2		T5	1		T6	1
valid_sources[0x6f]	1631	1			T4	1		T8	1		T14	2
valid_sources[0x70]	2442	1			T4	2		T14	8		T15	2
valid_sources[0x71]	1587	1			T3	2		T5	1		T6	1
valid_sources[0x72]	1756	1			T5	1		T10	164		T15	5
valid_sources[0x73]	1910	1			T3	1		T5	1		T8	1
valid_sources[0x74]	2066	1			T3	1		T4	1		T15	9
valid_sources[0x75]	1827	1			T4	3		T6	4		T8	1
valid_sources[0x76]	5117	1			T6	1		T8	1		T15	2
valid_sources[0x77]	1824	1			T1	31		T3	2		T14	6
valid_sources[0x78]	1535	1			T5	1		T6	1		T15	4
valid_sources[0x79]	1690	1			T5	1		T6	1		T8	2
valid_sources[0x7a]	2917	1			T6	4		T8	1		T14	17
valid_sources[0x7b]	1957	1			T4	2		T5	1		T14	3
valid_sources[0x7c]	2002	1			T15	5		T16	6		T36	3
valid_sources[0x7d]	1830	1			T4	4		T6	2		T8	3
valid_sources[0x7e]	1883	1			T4	1		T5	3		T6	3
valid_sources[0x7f]	3140	1			T3	3		T6	1		T8	2
valid_sources[0x80]	2142	1			T6	1		T8	1		T14	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

75348

1

T1

9

T2

1

T3

15

values[0x0]

all_enables

biggest_size

49324

1

T1

1

T2

2

T3

12

values[0x1]

all_enables

biggest_size

27561

1

T3

3

T4

6

T5

6