Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	18253463	14884	0	0
intr_enable_rd_A	18253463	31724	0	0
reset_en_rd_A	18253463	1611	0	0
reset_en_regwen_rd_A	18253463	1319	0	0
wake_info_capture_dis_rd_A	18253463	1354	0	0
wakeup_en_rd_A	18253463	2601	0	0
wakeup_en_regwen_rd_A	18253463	1291	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18253463	14884	0	0
T22	8840	0	0	0
T24	96378	5	0	0
T25	0	45	0	0
T26	0	33	0	0
T48	0	13	0	0
T49	0	8	0	0
T50	0	14	0	0
T80	4162	0	0	0
T81	1467	0	0	0
T82	6461	0	0	0
T83	0	62	0	0
T93	1223	0	0	0
T94	2628	0	0	0
T95	4580	0	0	0
T96	7595	0	0	0
T97	8205	0	0	0
T131	0	1	0	0
T132	0	29	0	0
T133	0	10	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18253463	31724	0	0
T2	1428	2	0	0
T3	4866	0	0	0
T4	8382	74	0	0
T5	1901	0	0	0
T6	5634	0	0	0
T7	625	0	0	0
T8	6742	71	0	0
T9	2965	0	0	0
T10	10263	0	0	0
T13	0	21	0	0
T14	26140	0	0	0
T24	0	895	0	0
T28	0	9	0	0
T79	0	10	0	0
T80	0	54	0	0
T95	0	116	0	0
T134	0	6	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18253463	1611	0	0
T22	8840	0	0	0
T24	96378	21	0	0
T45	0	12	0	0
T80	4162	0	0	0
T81	1467	0	0	0
T82	6461	0	0	0
T83	0	39	0	0
T93	1223	0	0	0
T94	2628	0	0	0
T95	4580	0	0	0
T96	7595	0	0	0
T97	8205	0	0	0
T131	0	7	0	0
T135	0	16	0	0
T136	0	12	0	0
T137	0	4	0	0
T138	0	33	0	0
T139	0	1	0	0
T140	0	8	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18253463	1319	0	0
T22	8840	0	0	0
T24	96378	16	0	0
T45	0	8	0	0
T80	4162	0	0	0
T81	1467	0	0	0
T82	6461	0	0	0
T83	0	45	0	0
T93	1223	0	0	0
T94	2628	0	0	0
T95	4580	0	0	0
T96	7595	0	0	0
T97	8205	0	0	0
T99	0	1	0	0
T131	0	3	0	0
T135	0	10	0	0
T136	0	18	0	0
T137	0	6	0	0
T138	0	57	0	0
T139	0	14	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18253463	1354	0	0
T22	8840	0	0	0
T24	96378	10	0	0
T80	4162	0	0	0
T81	1467	0	0	0
T82	6461	0	0	0
T83	0	43	0	0
T93	1223	0	0	0
T94	2628	0	0	0
T95	4580	0	0	0
T96	7595	0	0	0
T97	8205	0	0	0
T131	0	8	0	0
T135	0	6	0	0
T136	0	23	0	0
T137	0	14	0	0
T138	0	45	0	0
T139	0	6	0	0
T140	0	3	0	0
T141	0	15	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18253463	2601	0	0
T22	8840	0	0	0
T24	96378	24	0	0
T45	0	9	0	0
T80	4162	0	0	0
T81	1467	0	0	0
T82	6461	0	0	0
T83	0	35	0	0
T93	1223	0	0	0
T94	2628	0	0	0
T95	4580	0	0	0
T96	7595	0	0	0
T97	8205	0	0	0
T99	0	5	0	0
T131	0	3	0	0
T135	0	9	0	0
T136	0	16	0	0
T138	0	33	0	0
T139	0	12	0	0
T140	0	5	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18253463	1291	0	0
T22	8840	0	0	0
T24	96378	8	0	0
T45	0	9	0	0
T80	4162	0	0	0
T81	1467	0	0	0
T82	6461	0	0	0
T83	0	29	0	0
T93	1223	0	0	0
T94	2628	0	0	0
T95	4580	0	0	0
T96	7595	0	0	0
T97	8205	0	0	0
T99	0	5	0	0
T131	0	11	0	0
T135	0	26	0	0
T136	0	20	0	0
T137	0	11	0	0
T138	0	35	0	0
T139	0	19	0	0