Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	52909542	108936	0	0
StatusRise_A	52909542	122316	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52909542	108936	0	0
T1	4980	6	0	0
T2	4284	3	0	0
T3	14598	20	0	0
T4	25146	69	0	0
T5	5703	36	0	0
T6	16902	73	0	0
T7	1875	3	0	0
T8	20226	3	0	0
T9	8895	0	0	0
T10	30789	28	0	0
T14	0	210	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52909542	122316	0	0
T1	4980	9	0	0
T2	4284	5	0	0
T3	14598	22	0	0
T4	25146	75	0	0
T5	5703	38	0	0
T6	16902	79	0	0
T7	1875	9	0	0
T8	20226	6	0	0
T9	8895	15	0	0
T10	30789	30	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	17636514	40582	0	0
StatusRise_A	17636514	45396	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17636514	40582	0	0
T1	1660	2	0	0
T2	1428	1	0	0
T3	4866	8	0	0
T4	8382	23	0	0
T5	1901	13	0	0
T6	5634	27	0	0
T7	625	1	0	0
T8	6742	1	0	0
T9	2965	0	0	0
T10	10263	10	0	0
T14	0	87	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17636514	45396	0	0
T1	1660	3	0	0
T2	1428	2	0	0
T3	4866	9	0	0
T4	8382	25	0	0
T5	1901	14	0	0
T6	5634	29	0	0
T7	625	3	0	0
T8	6742	2	0	0
T9	2965	5	0	0
T10	10263	11	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	17636514	40583	0	0
StatusRise_A	17636514	45398	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17636514	40583	0	0
T1	1660	2	0	0
T2	1428	1	0	0
T3	4866	8	0	0
T4	8382	23	0	0
T5	1901	13	0	0
T6	5634	27	0	0
T7	625	1	0	0
T8	6742	1	0	0
T9	2965	0	0	0
T10	10263	10	0	0
T14	0	87	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17636514	45398	0	0
T1	1660	3	0	0
T2	1428	2	0	0
T3	4866	9	0	0
T4	8382	25	0	0
T5	1901	14	0	0
T6	5634	29	0	0
T7	625	3	0	0
T8	6742	2	0	0
T9	2965	5	0	0
T10	10263	11	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	17636514	27771	0	0
StatusRise_A	17636514	31522	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17636514	27771	0	0
T1	1660	2	0	0
T2	1428	1	0	0
T3	4866	4	0	0
T4	8382	23	0	0
T5	1901	10	0	0
T6	5634	19	0	0
T7	625	1	0	0
T8	6742	1	0	0
T9	2965	0	0	0
T10	10263	8	0	0
T14	0	36	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17636514	31522	0	0
T1	1660	3	0	0
T2	1428	1	0	0
T3	4866	4	0	0
T4	8382	25	0	0
T5	1901	10	0	0
T6	5634	21	0	0
T7	625	3	0	0
T8	6742	2	0	0
T9	2965	5	0	0
T10	10263	8	0	0