Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

41                      
42         1/1            always_comb reset_or_disable = !rst_ni || disable_sva;
           Tests:       T1 T2 T3 
43         1/1            always_comb esc_reset_or_disable = !rst_esc_ni || disable_sva;
           Tests:       T1 T2 T3 
44         1/1            always_comb slow_reset_or_disable = !rst_slow_ni || disable_sva;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	17637101	10268	0	0
EscTimeoutStoppedByClReset_A	17636514	2440552	0	0
EscTimeoutTriggersReset_A	3818876	428	0	0
RomAllowActiveState_A	17636514	44983	0	0
RomAllowCheckGoodState_A	17636514	45033	0	0
RomBlockActiveState_A	17636514	35516	0	0
RomBlockCheckGoodState_A	17636514	400967	0	0
RomIntgChkDisFalse_A	17636514	17111496	0	0
RomIntgChkDisTrue_A	17636514	104314	0	0
RstreqChkEsctimeout_A	17636514	3238	0	0
RstreqChkFsmterm_A	17636514	140	0	0
RstreqChkGlbesc_A	17636514	3238	0	0
RstreqChkMainpd_A	17636514	776249	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17637101	10268	0	0
T7	625	7	0	0
T8	6743	0	0	0
T9	2965	0	0	0
T10	10263	0	0	0
T11	10488	422	0	0
T12	0	9	0	0
T13	2926	0	0	0
T14	26140	0	0	0
T15	16791	0	0	0
T18	1483	0	0	0
T29	8523	0	0	0
T37	0	94	0	0
T85	0	1	0	0
T142	0	73	0	0
T143	0	44	0	0
T144	0	514	0	0
T145	0	19	0	0
T146	0	110	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17636514	2440552	0	0
T1	1660	30	0	0
T2	1428	98	0	0
T3	4866	330	0	0
T4	8382	782	0	0
T5	1901	13	0	0
T6	5634	784	0	0
T7	625	20	0	0
T8	6742	26	0	0
T9	2965	71	0	0
T10	10263	1888	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3818876	428	0	0
T7	398	7	0	0
T8	489	0	0	0
T9	295	0	0	0
T10	1033	0	0	0
T11	154	5	0	0
T12	0	4	0	0
T13	428	0	0	0
T14	5703	0	0	0
T15	7322	0	0	0
T18	638	0	0	0
T29	809	0	0	0
T37	0	5	0	0
T85	0	4	0	0
T142	0	6	0	0
T143	0	5	0	0
T144	0	6	0	0
T147	0	2	0	0
T148	0	2	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17636514	44983	0	0
T1	1660	3	0	0
T2	1428	2	0	0
T3	4866	9	0	0
T4	8382	25	0	0
T5	1901	14	0	0
T6	5634	29	0	0
T7	625	3	0	0
T8	6742	2	0	0
T9	2965	5	0	0
T10	10263	11	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17636514	45033	0	0
T1	1660	3	0	0
T2	1428	2	0	0
T3	4866	9	0	0
T4	8382	25	0	0
T5	1901	14	0	0
T6	5634	29	0	0
T7	625	3	0	0
T8	6742	2	0	0
T9	2965	5	0	0
T10	10263	11	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17636514	35516	0	0
T13	2925	459	0	0
T16	13676	0	0	0
T21	21502	0	0	0
T27	0	5	0	0
T28	0	66	0	0
T29	8522	0	0	0
T32	3909	0	0	0
T38	3119	0	0	0
T39	1226	0	0	0
T41	1513	0	0	0
T78	986	0	0	0
T79	2863	0	0	0
T89	0	1171	0	0
T91	0	9	0	0
T149	0	1208	0	0
T150	0	253	0	0
T151	0	932	0	0
T152	0	311	0	0
T153	0	329	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17636514	400967	0	0
T6	5634	344	0	0
T7	625	0	0	0
T8	6742	0	0	0
T9	2965	0	0	0
T10	10263	0	0	0
T11	10488	0	0	0
T13	2925	463	0	0
T14	26140	2244	0	0
T15	16791	1196	0	0
T18	1482	0	0	0
T24	0	826	0	0
T27	0	1228	0	0
T33	0	251	0	0
T36	0	2277	0	0
T97	0	161	0	0
T154	0	1468	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17636514	17111496	0	0
T1	1660	1598	0	0
T2	1428	1342	0	0
T3	4866	4769	0	0
T4	8382	8233	0	0
T5	1901	1851	0	0
T6	5634	5471	0	0
T7	625	464	0	0
T8	6742	6678	0	0
T9	2965	2643	0	0
T10	10263	10181	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17636514	104314	0	0
T11	10488	0	0	0
T13	2925	107	0	0
T14	26140	1129	0	0
T15	16791	0	0	0
T18	1482	0	0	0
T27	0	416	0	0
T28	0	91	0	0
T29	8522	0	0	0
T38	3119	0	0	0
T39	1226	0	0	0
T41	1513	0	0	0
T78	986	0	0	0
T89	0	320	0	0
T91	0	286	0	0
T149	0	1376	0	0
T150	0	750	0	0
T155	0	2667	0	0
T156	0	2383	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17636514	3238	0	0
T4	8382	10	0	0
T5	1901	0	0	0
T6	5634	0	0	0
T7	625	1	0	0
T8	6742	0	0	0
T9	2965	4	0	0
T10	10263	0	0	0
T11	0	2	0	0
T12	0	1	0	0
T13	0	3	0	0
T14	26140	0	0	0
T15	16791	0	0	0
T18	1482	0	0	0
T21	0	10	0	0
T29	0	7	0	0
T38	0	6	0	0
T39	0	2	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17636514	140	0	0
T12	823	0	0	0
T17	1037	0	0	0
T19	1344	0	0	0
T21	21502	20	0	0
T22	0	20	0	0
T23	0	40	0	0
T30	0	40	0	0
T31	0	20	0	0
T32	3909	0	0	0
T33	13324	0	0	0
T34	1804	0	0	0
T35	980	0	0	0
T36	33624	0	0	0
T37	9533	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17636514	3238	0	0
T4	8382	10	0	0
T5	1901	0	0	0
T6	5634	0	0	0
T7	625	1	0	0
T8	6742	0	0	0
T9	2965	4	0	0
T10	10263	0	0	0
T11	0	2	0	0
T12	0	1	0	0
T13	0	3	0	0
T14	26140	0	0	0
T15	16791	0	0	0
T18	1482	0	0	0
T21	0	10	0	0
T29	0	7	0	0
T38	0	6	0	0
T39	0	2	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17636514	776249	0	0
T4	8382	650	0	0
T5	1901	0	0	0
T6	5634	531	0	0
T7	625	0	0	0
T8	6742	0	0	0
T9	2965	0	0	0
T10	10263	0	0	0
T14	26140	3024	0	0
T15	16791	1488	0	0
T18	1482	16	0	0
T19	0	6	0	0
T29	0	179	0	0
T33	0	1086	0	0
T38	0	426	0	0
T39	0	67	0	0