Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	363633	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

144198

1

T1

17

T2

19

T3

44

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	266118	1			T1	25		T2	50		T3	122
values[0x0]	120536	1			T1	6		T2	20		T3	24
values[0x1]	121177	1			T1	4		T2	27		T3	38

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	287506	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

220325

1

T1

18

T2

35

T3

71

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1533	1			T1	1		T8	12		T14	7
valid_sources[0x01]	2299	1			T10	1		T13	9		T14	3
valid_sources[0x02]	1839	1			T2	2		T3	1		T10	10
valid_sources[0x03]	2410	1			T14	7		T37	1		T31	3
valid_sources[0x04]	1980	1			T2	2		T8	11		T37	4
valid_sources[0x05]	2815	1			T3	1		T14	1		T37	4
valid_sources[0x06]	1682	1			T14	6		T37	2		T39	18
valid_sources[0x07]	1524	1			T3	3		T14	3		T36	1
valid_sources[0x08]	2757	1			T14	8		T36	2		T37	8
valid_sources[0x09]	1942	1			T14	4		T59	1		T37	4
valid_sources[0x0a]	4447	1			T4	9		T13	2		T14	4
valid_sources[0x0b]	1545	1			T3	7		T14	2		T59	6
valid_sources[0x0c]	1646	1			T2	1		T3	1		T13	2
valid_sources[0x0d]	1568	1			T2	4		T10	4		T13	3
valid_sources[0x0e]	1490	1			T3	1		T10	1		T13	2
valid_sources[0x0f]	1396	1			T14	2		T37	3		T73	2
valid_sources[0x10]	1659	1			T3	6		T10	4		T13	3
valid_sources[0x11]	1653	1			T3	1		T7	1		T13	4
valid_sources[0x12]	1687	1			T13	1		T12	63		T14	1
valid_sources[0x13]	1492	1			T2	2		T14	9		T37	2
valid_sources[0x14]	1445	1			T4	4		T37	3		T39	1
valid_sources[0x15]	1656	1			T10	4		T14	5		T36	5
valid_sources[0x16]	2372	1			T2	1		T4	5		T28	1
valid_sources[0x17]	1611	1			T4	3		T28	6		T14	6
valid_sources[0x18]	1560	1			T14	7		T59	1		T37	3
valid_sources[0x19]	1777	1			T14	2		T36	1		T37	2
valid_sources[0x1a]	2491	1			T3	2		T14	6		T37	6
valid_sources[0x1b]	1711	1			T3	2		T4	19		T14	3
valid_sources[0x1c]	1463	1			T14	3		T59	6		T37	1
valid_sources[0x1d]	1468	1			T4	2		T8	12		T14	6
valid_sources[0x1e]	1561	1			T1	1		T2	2		T10	2
valid_sources[0x1f]	2026	1			T2	1		T14	2		T36	2
valid_sources[0x20]	1780	1			T10	6		T14	5		T59	2
valid_sources[0x21]	2026	1			T2	1		T14	3		T37	3
valid_sources[0x22]	2390	1			T2	1		T14	3		T37	5
valid_sources[0x23]	1533	1			T3	1		T14	1		T37	4
valid_sources[0x24]	1577	1			T13	2		T14	4		T37	8
valid_sources[0x25]	1569	1			T3	3		T8	6		T28	7
valid_sources[0x26]	1709	1			T3	2		T10	1		T14	3
valid_sources[0x27]	1948	1			T2	1		T4	17		T10	2
valid_sources[0x28]	1645	1			T4	8		T13	1		T28	2
valid_sources[0x29]	1643	1			T14	1		T59	1		T37	5
valid_sources[0x2a]	1644	1			T2	4		T10	2		T13	13
valid_sources[0x2b]	2231	1			T14	2		T59	1		T37	2
valid_sources[0x2c]	1377	1			T36	1		T37	4		T31	2
valid_sources[0x2d]	2137	1			T14	1		T36	1		T37	3
valid_sources[0x2e]	1523	1			T14	1		T37	5		T38	1
valid_sources[0x2f]	1516	1			T1	1		T14	2		T37	2
valid_sources[0x30]	2281	1			T2	1		T10	3		T13	2
valid_sources[0x31]	2586	1			T14	2		T59	4		T37	2
valid_sources[0x32]	5290	1			T32	6		T39	7		T73	6
valid_sources[0x33]	1942	1			T3	2		T4	8		T8	12
valid_sources[0x34]	2762	1			T10	1		T13	1		T14	6
valid_sources[0x35]	1602	1			T2	4		T10	1		T14	4
valid_sources[0x36]	1709	1			T13	4		T14	8		T37	4
valid_sources[0x37]	1428	1			T4	2		T10	3		T28	5
valid_sources[0x38]	1519	1			T1	1		T4	9		T14	1
valid_sources[0x39]	2481	1			T10	6		T13	1		T14	5
valid_sources[0x3a]	2837	1			T3	1		T28	2		T14	5
valid_sources[0x3b]	1605	1			T8	12		T14	4		T36	2
valid_sources[0x3c]	2114	1			T10	6		T14	1		T36	1
valid_sources[0x3d]	1534	1			T14	3		T37	5		T31	1
valid_sources[0x3e]	1635	1			T4	6		T14	7		T37	4
valid_sources[0x3f]	1831	1			T13	3		T14	2		T36	2
valid_sources[0x40]	2203	1			T3	5		T14	2		T36	2
valid_sources[0x41]	1637	1			T14	3		T37	4		T39	3
valid_sources[0x42]	2182	1			T14	10		T37	2		T73	1
valid_sources[0x43]	2515	1			T4	7		T14	1		T36	1
valid_sources[0x44]	1444	1			T3	2		T4	4		T10	1
valid_sources[0x45]	1695	1			T2	1		T3	3		T14	4
valid_sources[0x46]	1445	1			T28	1		T14	1		T36	1
valid_sources[0x47]	1908	1			T3	2		T13	8		T14	3
valid_sources[0x48]	1532	1			T14	1		T37	3		T31	1
valid_sources[0x49]	1543	1			T1	1		T3	2		T10	1
valid_sources[0x4a]	3782	1			T14	1		T36	1		T59	7
valid_sources[0x4b]	1404	1			T3	2		T14	1		T37	1
valid_sources[0x4c]	1725	1			T14	3		T37	6		T31	1
valid_sources[0x4d]	1538	1			T1	1		T3	8		T14	2
valid_sources[0x4e]	1601	1			T14	2		T59	1		T37	4
valid_sources[0x4f]	1869	1			T4	24		T14	1		T37	1
valid_sources[0x50]	1694	1			T3	3		T13	3		T14	5
valid_sources[0x51]	4380	1			T10	1		T14	5		T37	4
valid_sources[0x52]	1697	1			T3	6		T14	2		T36	1
valid_sources[0x53]	1565	1			T3	6		T14	2		T37	9
valid_sources[0x54]	2991	1			T1	1		T4	2		T37	4
valid_sources[0x55]	1771	1			T14	2		T36	1		T59	4
valid_sources[0x56]	1723	1			T17	1		T28	2		T37	6
valid_sources[0x57]	1605	1			T1	1		T10	1		T13	5
valid_sources[0x58]	1652	1			T1	1		T3	1		T37	1
valid_sources[0x59]	1781	1			T3	1		T14	4		T59	2
valid_sources[0x5a]	1429	1			T10	3		T14	5		T37	3
valid_sources[0x5b]	2784	1			T14	1		T36	4		T33	1
valid_sources[0x5c]	1612	1			T13	1		T14	2		T59	1
valid_sources[0x5d]	2162	1			T3	4		T14	7		T36	1
valid_sources[0x5e]	1407	1			T1	1		T28	1		T14	4
valid_sources[0x5f]	1520	1			T2	3		T10	4		T28	3
valid_sources[0x60]	3970	1			T2	1		T10	1		T28	3
valid_sources[0x61]	2971	1			T2	3		T37	3		T38	1
valid_sources[0x62]	1415	1			T2	3		T14	6		T36	6
valid_sources[0x63]	1559	1			T2	1		T6	1		T8	11
valid_sources[0x64]	1537	1			T3	2		T10	1		T28	1
valid_sources[0x65]	1598	1			T1	2		T2	6		T3	1
valid_sources[0x66]	1480	1			T14	3		T59	2		T37	6
valid_sources[0x67]	2117	1			T10	2		T13	5		T14	3
valid_sources[0x68]	1452	1			T13	3		T14	5		T36	3
valid_sources[0x69]	1648	1			T3	1		T10	3		T14	2
valid_sources[0x6a]	1805	1			T3	2		T13	7		T14	3
valid_sources[0x6b]	2194	1			T10	1		T14	1		T38	1
valid_sources[0x6c]	2402	1			T14	4		T37	5		T73	3
valid_sources[0x6d]	4612	1			T9	1		T14	5		T37	6
valid_sources[0x6e]	1601	1			T1	1		T10	1		T13	2
valid_sources[0x6f]	1732	1			T14	4		T59	1		T37	3
valid_sources[0x70]	1577	1			T1	1		T3	2		T14	6
valid_sources[0x71]	1609	1			T14	2		T36	1		T37	6
valid_sources[0x72]	3651	1			T28	7		T14	4		T59	1
valid_sources[0x73]	1669	1			T1	1		T3	3		T14	5
valid_sources[0x74]	2688	1			T2	3		T3	1		T14	5
valid_sources[0x75]	3555	1			T13	1		T14	7		T37	4
valid_sources[0x76]	1504	1			T3	6		T4	3		T28	1
valid_sources[0x77]	1523	1			T10	1		T14	6		T37	1
valid_sources[0x78]	2705	1			T4	5		T28	3		T14	8
valid_sources[0x79]	2853	1			T14	7		T36	1		T37	4
valid_sources[0x7a]	1475	1			T4	31		T14	10		T59	10
valid_sources[0x7b]	1644	1			T3	5		T14	2		T36	1
valid_sources[0x7c]	1601	1			T3	1		T14	4		T36	1
valid_sources[0x7d]	1562	1			T14	5		T37	4		T31	2
valid_sources[0x7e]	2380	1			T5	190		T14	2		T36	2
valid_sources[0x7f]	2137	1			T28	1		T14	2		T37	6
valid_sources[0x80]	1514	1			T1	2		T14	7		T37	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

71971

1

T1

14

T2

11

T3

29

values[0x0]

all_enables

biggest_size

46241

1

T1

2

T2

5

T3

8

values[0x1]

all_enables

biggest_size

25986

1

T1

1

T2

3

T3

7